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Reconfigurable split data caches

Afrin Naz, Krishna Kavi, JungHwan Oh, Pierfrancesco Foglia
2007 Proceedings of the 2007 ACM symposium on Applied computing - SAC '07  
This paper shows that even very small reconfigurable data caches, when split to serve data streams exhibiting temporal and spatial localities, can improve performance of embedded applications without consuming  ...  We use benchmark programs from the MiBench suite to show that our cache organization outperforms an 8k unified data cache in terms of miss rates, access times, energy consumption and silicon area.  ...  In future we will explore a combined instruction and (our split) data caches in reconfiguring choices.  ... 
doi:10.1145/1244002.1244160 dblp:conf/sac/NazKOF07 fatcat:kkwrktmdwfd2fhe6fhman4vrty

Flux Caches: What Are They and Are They Useful? [chapter]

Georgi N. Gaydadjiev, Stamatis Vassiliadis
2005 Lecture Notes in Computer Science  
Consequently program (data and instruction) dynamic behavior determines the cache hardware design.  ...  Contrary to the traditional approaches, processors designed with flux caches instead of assuming a hardwired cache organization change their cache "design" on program demand.  ...  split instruction/data caches of equal sizes.  ... 
doi:10.1007/11512622_11 fatcat:kniuu6xesrdkfljf47zteibkli

Configurable memory systems for embedded many-core processors [article]

Daniel Bates, Alex Chadwick, Robert Mullins
2016 arXiv   pre-print
We then present a case study of AES encryption and decryption, and find that a custom memory configuration can almost double performance, with further benefits being achieved by specialising the task of  ...  We explore a range of different configuration options and show that a reconfigurable design can make better use of the resources available to it than any fixed implementation, and provide large improvements  ...  Figure 5 compares the performance of two 8-bank configurations and two 4-bank configurations. In each case, a unified cache and a cache split evenly between instructions and data is considered.  ... 
arXiv:1601.00894v2 fatcat:wrku2p6jvrgqbg6fslg725ifk4

Dynamically managing the communication-parallelism trade-off in future clustered processors

Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
2003 Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03  
As a result of the emergence of this trade-off between communication and parallelism, a subset of the total on-chip clusters is optimal for performance.  ...  We also show that the use of additional hardware and reconfiguration at basic block boundaries can achieve average improvements of 15%.  ...  For a 4-way wordinterleaved cache, the data array is split into four banks and each bank can service one request every cycle.  ... 
doi:10.1145/859618.859650 fatcat:65mb7apno5ajxkwevbozfjbnki

Dynamically managing the communication-parallelism trade-off in future clustered processors

Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
2003 SIGARCH Computer Architecture News  
As a result of the emergence of this trade-off between communication and parallelism, a subset of the total on-chip clusters is optimal for performance.  ...  We also show that the use of additional hardware and reconfiguration at basic block boundaries can achieve average improvements of 15%.  ...  For a 4-way wordinterleaved cache, the data array is split into four banks and each bank can service one request every cycle.  ... 
doi:10.1145/871656.859650 fatcat:wyly77sngvfajcympyzpuclqvy

Dynamically managing the communication-parallelism trade-off in future clustered processors

Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
2003 Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03  
As a result of the emergence of this trade-off between communication and parallelism, a subset of the total on-chip clusters is optimal for performance.  ...  We also show that the use of additional hardware and reconfiguration at basic block boundaries can achieve average improvements of 15%.  ...  For a 4-way wordinterleaved cache, the data array is split into four banks and each bank can service one request every cycle.  ... 
doi:10.1145/859648.859650 fatcat:hleo6ob4sbdxdpy26g4iaadej4

AMOEBA: A Coarse Grained Reconfigurable Architecture for Dynamic GPU Scaling [article]

Xianwei Cheng, Hui Zhao, Mahmut Kandemir, Beilei Jiang, Gayatri Mehta
2019 arXiv   pre-print
We then propose AMOEBA, a solution to GPU scaling through reconfigurable SM cores.  ...  AMOEBA also enables dynamic creation of heterogeneous SMs through independent fusing or splitting.  ...  NoC Impact Dynamics of Core Fusion and Splitting To observe the dynamics of switching between fusing and splitting, we studied the status of five SMs in benchmark RAY.  ... 
arXiv:1911.03364v1 fatcat:tcmbakgikjhtdl2khxzei3zf74

EvoCaches: Application-specific Adaptation of Cache Mappings

Paul Kaufmann, Christian Plessl, Marco Platzner
2009 2009 NASA/ESA Conference on Adaptive Hardware and Systems  
Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for  ...  We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric.  ...  The configuration is shown in Figure 4 and includes a split first level cache and a unified second level cache.  ... 
doi:10.1109/ahs.2009.26 dblp:conf/ahs/KaufmannPP09 fatcat:tldvc5skt5glxbtxd6n4csuk5i

A framework for efficient cache resizing

Georgios Keramidas, Chrysovalantis Datsios, Stefanos Kaxiras
2012 2012 International Conference on Embedded Computer Systems (SAMOS)  
We present a novel framework to dynamically reconfigure on-chip memory resources according to the changing behavior of the running applications.  ...  ., resizing) of the on-chip caches targeting both performance and power efficiency.  ...  In this work, for simplicity, we assume that in all the L1 cache organizations studied in this paper, each subarray (tag or data) consists of eight cache sets and the set-associative caches are split vertically  ... 
doi:10.1109/samos.2012.6404160 dblp:conf/samos/KeramidasDK12 fatcat:ppbgoemj2vhpvjc4ispc2jto2m

Compiler Optimizations for Adaptive EPIC Processors [chapter]

Krishna V. Palem, Surendranath Talla, Weng-Fai Wong
2001 Lecture Notes in Computer Science  
In an earlier paper, we proposed a machine architecture for achieving this reconfigurability and compilation issues that such an architecture will face.  ...  Advances in VLSI technology have lead to a tremendous increase in the density and number of devices that can be manufactured in a single microchip.  ...  Pruning involves (a) determining the set of live ranges to split and, (b) determining the right split points for the selected live ranges.  ... 
doi:10.1007/3-540-45449-7_18 fatcat:32lfxjsqofhk3m2h4mdtzza53u

SAD Prefetching for MPEG4 Using Flux Caches [chapter]

Georgi N. Gaydadjiev, Stamatis Vassiliadis
2006 Lecture Notes in Computer Science  
In this paper, we consider flux caches prefetching and a media application. We analyze the MPEG4 encoder workload with realistic data set in a scenario representative for the embedded systems domain.  ...  Our study shows that different well known data prefetch mechanisms can gain little reduction in the cache miss ratios when applied on the complete MPEG4 application.  ...  For our experimental cache we use 2k split instruction and data direct mapped cache with 16 byte lines with no sub-blocks.  ... 
doi:10.1007/11796435_26 fatcat:g6r6nqydtbenvngk246so3676e

A survey of dual data cache systems

Z. Sustran, S. Stojanovic, G. Rakocevic, V. M. Milutinovic, M. Valero
2012 2012 IEEE International Conference on Industrial Technology  
DDC systems divide data according to their access patterns and use different caching strategies on them.  ...  The second part of this paper represents a survey of the existing solutions classified according to proposed criteria, presenting their organization, benefits, shortcomings, and intended use.  ...  The Reconfigurable Split Data Cache Naz, Kavi, Oh, and Foglia in [6] present the reconfigurable split data cache (RSDC) architecture for embedded systems, in order to accomplish a better utilization  ... 
doi:10.1109/icit.2012.6209979 fatcat:s3q4esk4azfetmvd3zdczxfg6a

Decision Tree-Based Adaptive Reconfigurable Cache Scheme

Wei Zhu, Xiaoyang Zeng
2021 Algorithms  
To solve this problem, we propose a real-time adaptive reconfigurable cache based on the decision tree algorithm, which can optimize the average memory access time of cache without modifying the cache  ...  Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system.  ...  Data Availability Statement: Not applicable. Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/a14060176 fatcat:bse76qcqonb2hjimusvad22jza

Performance Advantage of Reconfigurable Cache Design on Multicore Processor Systems

Jie Tao, Marcel Kunze, Fabian Nowak, Rainer Buchty, Wolfgang Karl
2008 International journal of parallel programming  
This work studies a reconfigurable cache architecture that can be dynamically configured for meeting the individual demand of running applications.  ...  This motivated us to go a step further and develop a hardware prototype of this novel architecture.  ...  In addition, we integrate a monitor module on the chip to trace the cache events, and the instruction and data address of theses events.  ... 
doi:10.1007/s10766-008-0075-4 fatcat:upasvelaqfgcbc2t2r3h5h4y24

MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy

Shekhar Srikantaiah, Emre Kultursay, Tao Zhang, Mahmut Kandemir, Mary Jane Irwin, Yuan Xie
2011 2011 IEEE 17th International Symposium on High Performance Computer Architecture  
Starting from per-core L2 and L3 cache slices as the basic design point, MorphCache alters the cache topology dynamically by merging or splitting cache slices and modifying the accessibility of different  ...  In this paper, we propose MorphCache, a Reconfigurable Adaptive Multi-level Cache hierarchy.  ...  Î AE Ò Ó Õ Ö Î Ì Ó Õ × Ø Î Ø Å Ò Ù Ú Ù Ù Û Ü Ý Þ ß à á â ã ä å â ae ments a variety of policies including those for fair cache sharing and achieving differentiated instruction throughput.  ... 
doi:10.1109/hpca.2011.5749732 dblp:conf/hpca/SrikantaiahKZKIX11 fatcat:ywdcspyspvadhbhrfqyyhkxa6u
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