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Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite

Hussein Al-Zoubi, Aleksandar Milenkovic, Milena Milenkovic
2004 Proceedings of the 42nd annual Southeast regional conference on - ACM-SE 42  
, across wide range of cache sizes and organizations.  ...  Replacement policy, one of the key factors determining the effectiveness of a cache, becomes even more important with latest technological trends toward highly associative caches.  ...  OPT, LRU, Random, FIFO, and two pseudo LRU polices, treebased and MRU-based, have been studied on a wide range of cache organizations, varying cache size, associativity, and cache level.  ... 
doi:10.1145/986537.986601 dblp:conf/ACMse/Al-ZoubiMM04 fatcat:yy3nxllshzao7hpvbcmlol6cua

Instruction Cache Replacement Policies and Organizations

Smith, Goodman
1985 IEEE transactions on computers  
First the loop model is used to study replacement policies and cache organizations.  ...  Instruction cache replacement policies and organizations are analyzed both theoretically and experimentally. Theoretical analyses are based on a new model for cache references -the loop model.  ...  Chiang for program development work on the trace generator and cache simulator programs. A. L. Fisher offered helpful suggestions based on a preliminary version of this paper.  ... 
doi:10.1109/tc.1985.1676566 fatcat:mepcue4fyzed7irdpj2hs4stii

Understanding cache hierarchy interactions with a program-driven simulator

Leticia Pascual, Alejandro Torrentí, Julio Sahuquillo, José Flich
2007 Proceedings of the 2007 workshop on Computer architecture education - WCAE '07  
Students in computer organization/architecture courses face the problem of understanding how caches interact in a hierarchical organization.  ...  Also, students can perform interesting exercises where both the code and the impact of cache organization parameters on performance are analyzed globally.  ...  Acknowledgments Authors would like to thank instructors and students of the Computer Organization course for their useful comments to improve the quality of the proposed tool.  ... 
doi:10.1145/1275633.1275639 fatcat:y6glwgwg3zffzmda2uqgmoi7vi

An execution-driven simulation tool for teaching cache memories in introductory computer organization courses

Salvador Petit, Noel Tomás, Julio Sahuquillo, Ana Pont
2006 Proceedings of the 2006 workshop on Computer architecture education held in conjunction with the 33rd International Symposium on Computer Architecture - WCAE '06  
The tool allows, in an intuitive and easy way, to select a given cache organization and run step-by-step the code proposed while visualizing dynamic changes in the cache's state.  ...  Hence, students perform these exercises by means of the classic "paper and pencil" methodology.  ...  Acknowledgements This work has been partially supported by the Generalitat Valenciana under grant GV06/326 and by Spanish CICYT under Grant TIC2003-08154-C06-01.  ... 
doi:10.1145/1275620.1275628 dblp:conf/wcae/PetitTSP06 fatcat:oyifiq3tzfchdnfj6f2yuluvqu

Adaptive Insertion and Promotion Policies Based on Least Recently Used Replacement

Wenbing JIN, Xuanya LI, Yanyong YU, Yongzhi WANG
2013 IEICE transactions on information and systems  
A number of these approaches even change the organization of the existing cache design.  ...  AIP dynamically inserts a missed line in the middle of the cache list and promotes a reused line several steps left, realizing the combination of LRU and LFU policies deliberately under a single unified  ...  A recent study on Shepherd Cache [12] even changes the organization of the existing cache, leading to further verification and testing efforts for it.  ... 
doi:10.1587/transinf.e96.d.124 fatcat:hzt526y5gbfo5osmd3gkg6zh5m

The Influence of Cache Organization on E-learning Environments

Ayman Al-Nsour
2009 International Journal of Emerging Technologies in Learning (iJET)  
As a result of this work, we recommend the set associative cache memory organization with the Least Frequently Used (LFU) replacement policy, as this led to optimal performance in e-learning environments  ...  In particular, we study the influence of three cache organizations, namely fully associative, direct, and set associative caches.  ...  We study how worthwhile it would be to vary cache organizations in e-learning environments. Moreover, we study the sideeffects forced by the adopted cache replacement policy. II.  ... 
doi:10.3991/ijet.v4i2.652 fatcat:6segnbrjhjeo5igujeyluh6v54

LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors

Javier Lira, Carlos Molina, Antonio Gonzalez
2009 2009 IEEE International Conference on Computer Design  
This policy involves three key decisions when there is a miss: where to place a data block within the cache set, which data to evict from the cache set and finally, where to place the evicted data.  ...  This translates into an average IPC improvement of 8% and into an Energy per Instruction (EPI) reduction of 5%. 978-1-4244-5028-2/09/$25.00 ©2009 IEEE  ...  None of these studies properly addresses bank replacement policy in a CMP environment. VIII.  ... 
doi:10.1109/iccd.2009.5413142 dblp:conf/iccd/LiraMG09 fatcat:3vgjtp5obja5fn2h6zaoykubqi

Spim-Cache: A Pedagogical Tool for Teaching Cache Memories Through Code-Based Exercises

Julio Sahuquillo, Noel Tomas, Salvador Petit, Ana Pont
2007 IEEE Transactions on Education  
Cache memories represent a core topic in all computer organization and architecture courses offered at universities around the world.  ...  A valuable pedagogical help when studying cache memories is to perform exercises based on simple algorithms, which allow the identification of cache accesses, for instance, a program accessing the elements  ...  ACKNOWLEDGMENT The authors would like to thank the anonymous reviewers, instructors, and students of the Computer Organization course for their useful comments to improve the quality of the proposed tool  ... 
doi:10.1109/te.2007.900021 fatcat:4ocafg4rkrfsll4k5uvfwkj54y

Article summaries

A.R. Hurson, K.M. Kavi, B. Shirazi, B. Lee
1996 IEEE Parallel & Distributed Technology Systems & Applications  
Designers can increase architectural support for instruction-level parallelism to absorb such a massive hardware capacity; examples are superscalar and superpipeline machmes.'  ...  However, the single-instruction stream processing characteristic of the control-flow machine makes it inherently unsuitable to exploit superscalar and superpipeline architectures efficiently.2 This is  ...  ACKNOWLEDGMENTS This work has been supported in part by the National Science Foundation under Grants MIP-9622836 and MIP-9622593.  ... 
doi:10.1109/88.544436 fatcat:gghokp44izf65ocixorvsnjix4

Flux Caches: What Are They and Are They Useful? [chapter]

Georgi N. Gaydadjiev, Stamatis Vassiliadis
2005 Lecture Notes in Computer Science  
Contrary to the traditional approaches, processors designed with flux caches instead of assuming a hardwired cache organization change their cache "design" on program demand.  ...  In this paper, we introduce the concept of flux caches envisioned to improve processor performance by dynamically changing the cache organization and implementation.  ...  It is very likely that different applications may greatly benefit from replacement policy changes.  ... 
doi:10.1007/11512622_11 fatcat:kniuu6xesrdkfljf47zteibkli

Two Cooperative Partitions for the Lase Level Cache

Baozhong Yu, Zening Qu, Jianlang Ma, Tianzhou Chen
2011 Procedia Engineering  
Hence, improving the replacement policy is critical to the improvement of cache efficiency and the overall system performance.  ...  Currently the most widely used replacement policy in the last cache is the LRU algorithm.  ...  TCP-default and TCP-accessed are of the same size and are under the management of LRU replacement policy. They play the same role as conventional L2 cache.  ... 
doi:10.1016/j.proeng.2011.08.662 fatcat:u6zj4mjuivbcbiifxsw7cxc2ei

Using dead blocks as a virtual victim cache

Samira M. Khan, Daniel A. Jiménez, Doug Burger, Babak Falsafi
2010 Proceedings of the 19th international conference on Parallel architectures and compilation techniques - PACT '10  
A virtual victim cache in a 16-way set associative 2MB L2 cache reduces misses by 11.7%, yields an average speedup of 12.5% and improves cache efficiency by 15% on average, where cache efficiency is defined  ...  The pool of predicted dead blocks can be thought of as a virtual victim cache.  ...  For this study, we explore an organization that uses the idea of a skewed organization [22, 16] Figure 3 shows the difference in the design of the original and skewed reference trace predictors.  ... 
doi:10.1145/1854273.1854333 dblp:conf/IEEEpact/KhanJBF10 fatcat:pjrv7cd5urbijkb2o5k5j7s5cu

LRU-SEQ: a novel replacement policy for transition energy reduction in instruction caches

P. Kalla, X.S. Hu, J. Henkel
2003 ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)  
In this paper we present, as the first approach of its kind, a novel energy saving replacement policy called LRU-SEQ for instruction caches.  ...  Evaluation of the policy on various architectures in a system-level environment has shown that upto 23% energy savings can be obtained.  ...  Conclusions We presented a novel replacement policy LRU-SEQ for instruction caches.  ... 
doi:10.1109/iccad.2003.159733 fatcat:yvuuo4dl4jg3lg3uqf6wt7vwjy

Where replacement algorithms fail

Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras
2010 Proceedings of the 7th ACM international conference on Computing frontiers - CF '10  
In this paper, we thoroughly examine four recently proposed replacement policies: the Dynamic Insertion Policy (DIP), the Shepherd Cache (SC), the MLP-aware replacement, and the Instruction-based Reuse  ...  Cache placement and eviction, especially at the last level of the memory hierarchy, have received a flurry of research activity recently.  ...  ACKNOWLEDGEMENTS This work is supported by the EU-FP6 Integrated Project, Scalable computer ARChitecture (SARC), Contract No. 27648 and the EU-FP7 ICT Projects, "A highly efficient adaptive multiprocessor  ... 
doi:10.1145/1787275.1787316 dblp:conf/cf/KeramidasPK10 fatcat:uofbg5td4jdm5annb72ifvbjki

A new TCB cache to efficiently manage TCP sessions for web servers

Guangdeng Liao, Laxmi Bhuyan, Wei Wu, Heeyeol Yu, Steve R. King
2010 Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems - ANCS '10  
We carefully design the TCB cache along two important axes: cache indexing and cache replacement policies.  ...  Second, by leveraging characteristics of web sessions, we design a speculative cache replacement policy, which can effectively work on the TCB cache with two cache banks.  ...  ACKNOWLEDGMENTS The research was supported by NSF grants CCF-0811834, NEDG-0832108, CSR-0912850, and a grant from Intel Corporation.  ... 
doi:10.1145/1872007.1872039 dblp:conf/ancs/LiaoBWYK10 fatcat:w424uozhufgzzc24q642rd7asi
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