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ANDES: Evaluating mapping strategies with synthetic programs
1996
Journal of systems architecture
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MIMD runs on Sun workstations and it simulates the execution of message-passing parallel programs on arbitrary distributed memory multiprocessors. ...
MIMD and HASTE use simulators, not a real parallel system. ...
His research activities concern all aspects of the study of che impact of parallelism on the conception of efficient algorithms (namely, Model and Design of parallel algorithms, Scheduling and Mapping, ...
doi:10.1016/s1383-7621(96)00022-7
fatcat:ohryxhrexjg2tkqlha2ozgnxfq
Parallel Computation of a Maximum-Likelihood Estimator of a Physical Map
2001
Genetics
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The optimal probe ordering is determined using a stochastic optimization algorithm such as simulated annealing or microcanonical annealing. ...
Implementation and experimental results on a distributed-memory multiprocessor cluster running the parallel virtual machine (PVM) environment are presented using simulated and real hybridization data. ...
the kinetic energy PVM is based on a distributed-memory message-passing E k Ͼ 0 is represented by a demon or a collection of paradigm of parallel computing. ...
doi:10.1093/genetics/157.3.1021
fatcat:rkjm4hqrpray5p7bgqfkqyf7hy
Parallel computation of a maximum-likelihood estimator of a physical map
2001
Genetics
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The optimal probe ordering is determined using a stochastic optimization algorithm such as simulated annealing or microcanonical annealing. ...
Implementation and experimental results on a distributed-memory multiprocessor cluster running the parallel virtual machine (PVM) environment are presented using simulated and real hybridization data. ...
the kinetic energy PVM is based on a distributed-memory message-passing E k Ͼ 0 is represented by a demon or a collection of paradigm of parallel computing. ...
pmid:11238392
pmcid:PMC1461556
fatcat:meg4wkkpprfzzhu74qvmhgwo7a
Efficient CFD code implementation for the ARM-based Mont-Blanc architecture
2018
Future generations computer systems
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CFD code has been run on up to 128 ARM-based Mont-Blanc nodes. • An heterogeneous implementation has been developed to occupy the overall system. • A dynamic Tabu search load balance algorithm distributes ...
The latest Mont-Blanc prototypes use system-on-chip (SoC) devices that combine a CPU and a GPU sharing a common main memory. ...
Montoya, Annealing-based heuristics and genetic algorithms for circuit partitioning in parallel test generation, Future Gener. Comput. ...
doi:10.1016/j.future.2017.09.029
fatcat:rw7x7remm5e55l6uyrkxiwbhgy
PARTI primitives for unstructured and block structured problems
1992
Computing Systems in Engineering
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This paper describes a set of primitives (PARTI) developed to e ciently execute unstructured and block structured problems on distributed memory parallel machines. ...
We present experimental data from a 3-D unstructured Euler solver run on the Intel Touchstone Delta to demonstrate the usefulness of our methods. ...
This research was performed in part using the Intel Touchstone Delta System operated by Caltech on behalf of the Concurrent Supercomputing Consortium. ...
doi:10.1016/0956-0521(92)90096-2
fatcat:5jp32g7zmfhhxi3pqae4beyjwi
A domain decomposition strategy for alignment of multiple biological sequences on multiprocessor platforms
2009
Journal of Parallel and Distributed Computing
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2009 pre-print arXiv:0905.1744v1 fatcat:qw6xydcnfva4zbs72ptraq2wqe
The proposed algorithm has been implemented on a cluster of workstations using MPI library. ...
In particular, we propose a highly scalable algorithm, Sample-Align-D, for aligning biological sequences using Muscle system as the underlying heuristic. ...
Communication Cost The communication overhead is an important factor that dictates the performance of a distributed message passing parallel system. ...
doi:10.1016/j.jpdc.2009.03.006
fatcat:glqtxv4fabhihdrkqey4z4xdeu
Energy-Efficient Scheduling of Periodic Applications on Safety-Critical Time-Triggered Multiprocessor Systems
2018
Electronics
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Energy optimization for periodic applications running on safety/time-critical time-triggered multiprocessor systems has been studied recently. ...
To decrease the high complexity of MILP, we also develop a heuristic algorithm to efficiently find a high-quality solution in reasonable time. ...
The communication procedure among inter-core rely on message-passing [30] . ...
doi:10.3390/electronics7060098
fatcat:5bnssea54ffw3ff3s3uoqzxrb4
Parallel computing works!
1996
IEEE Parallel & Distributed Technology Systems & Applications
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These are several commercial systems that offer some or all of the features of Express, based on long-range communication by message passing: i) Mercury/Centaur JPL developed this message-passing system ...
The idea was that messages would be buffered on their node of origin until a synchronization point was reached when a single system call sent every message to its destination in one pass. ...
Initially, a small popula- An 11 x 9 array with block-linear rows (B = 2) and scattered columns on a 4 x 4 logical process grid. ...
doi:10.1109/mpdt.1996.7102339
fatcat:r6x46zu2pfd4rin4qpzt7ftqqq
Space-time scheduling of instruction-level parallelism on a raw machine
1998
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems - ASPLOS-VIII
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large amount of parallelism. ...
Compilation for instruction-level parallelism (ILP) on such distributed-resource machines requires both spatial instruction scheduling and traditional temporal instruction scheduling. ...
For large configurations, this greedy algorithm can be replaced by one with simulated annealing for better performance. ...
doi:10.1145/291069.291018
dblp:conf/asplos/LeeBFSBSA98
fatcat:bwsn74jmxbd6baz3y7hwi4p7cy
Space-time scheduling of instruction-level parallelism on a raw machine
1998
ACM SIGOPS Operating Systems Review
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for applications with parallelism within a basic block. ...
Compilation for instruction-level parallelism (ILP) on such distributed-resource machines requires both spatial instruction scheduling and traditional temporal instruction scheduling. ...
This greedy algorithm can be replaced by one with simulated annealing for better performance. ...
doi:10.1145/384265.291018
fatcat:dixm7e7hszb3zh6qa5slvkvxby
Space-time scheduling of instruction-level parallelism on a raw machine
1998
SIGPLAN notices
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for applications with parallelism within a basic block. ...
Compilation for instruction-level parallelism (ILP) on such distributed-resource machines requires both spatial instruction scheduling and traditional temporal instruction scheduling. ...
This greedy algorithm can be replaced by one with simulated annealing for better performance. ...
doi:10.1145/291006.291018
fatcat:hna7zwpzkzfovkfg2tn7lugw4m
Implementation and performance aspects of Kahn process networks
2010
ACM SIGMultimedia Records
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KPNs are a model of concurrency that relies exclusively on message passing, and that has some advantages over parallel programming tools in wide use today: simplicity, graphical representation, and determinism ...
understanding brought by this evaluation is significant not only in the context of the Kahn model, but also in the more general context of load-balancing (potentially distributed) applications written in message-passing ...
The plots exhibit a distinct pattern: the running time increases step-wise with the number of workers n, with jumps occurring when n mod 8 = 1. ...
doi:10.1145/1874413.1874418
fatcat:sm5wsqpyyfevtarf6336elhyny
Grid-Enabling an Efficient Algorithm for Demanding Global Optimization Problems in Genetic Analysis
2007
Third IEEE International Conference on e-Science and Grid Computing (e-Science 2007)
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We first describe how the algorithm used for global optimization in the standard, serial software is parallelized and implemented on a grid system. ...
Then, we also describe a parallelized version of the more elaborate global optimization algorithm DIRECT and show how this can be deployed on grid systems and other loosely-coupled architectures. ...
However, further development of algorithms and codes for multicore chips is needed to fully take advantage of the architectural properties of these systems. ...
doi:10.1109/e-science.2007.40
dblp:conf/eScience/JayawardenaH07
fatcat:ew5igzieunfwzfq32ushgcmbn4
The PARSEC benchmark suite
2008
Proceedings of the 17th international conference on Parallel architectures and compilation techniques - PACT '08
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Previous available benchmarks for multiprocessors have focused on high-performance computing applications and used a limited number of synchronization methods. ...
This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PAR-SEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). ...
They convinced skeptics and supported us so that a project the size of PARSEC could succeed. ...
doi:10.1145/1454115.1454128
dblp:conf/IEEEpact/BieniaKSL08
fatcat:mskdckm6urbknpxxt5c6hldlli
THE AMERICAN MUSEUM OF NATURAL HISTORY
1911
Science
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As with any optimization algorithm, two steps are performed, a down pass and an up pass (Algorithms 5.1 and 5.2). ...
For this reason, every optimization algorithm performs two steps, a down pass and an up pass (Algorithms 5.1 and 5.2). ...
PVM Parallel virtual machine; middleware that handles communication on a parallel processing cluster, such as a Beowulf. ...
doi:10.1126/science.33.839.142
pmid:17731786
fatcat:rktmdddq3jblpniceihkfymqji
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