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A Statistical Traffic Model for On-Chip Interconnection Networks

V. Soteriou, Hangsheng Wang, L. Peh
14th IEEE International Symposium on Modeling, Analysis, and Simulation  
In this paper we propose such an empirically-derived network on-chip traffic model for homogeneous NoCs.  ...  Though on-chip networks (a. k.a networks-on-chip (NoCs)) are becoming the de-facto scalable communication fabric in many-core systems-on-a-chip (SoCs) and chip multiprocessors (CMPs), no on-chip network  ...  for his help on compiling the RAW applications.  ... 
doi:10.1109/mascots.2006.9 dblp:conf/mascots/SoteriouWP06 fatcat:cai7laq7pnbw7kodvoesrubrza

A Generic Multi-Phase On-Chip Traffic Generation Environment

Antoine Scherrer, Antoine Fraboulet, Tanguy Risset
2006 IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)  
We present hereafter a framework for on-chip traffic generation and networks-on-chip performance evaluation.  ...  interconnect systems, and the capacity to produce stochastic traffic with advanced statistical properties.  ...  On Chip Traffic Modelling NoC performances are mainly evaluated with traffic generators (tg).  ... 
doi:10.1109/asap.2006.5 dblp:conf/asap/ScherrerFR06 fatcat:lbnd3zfz5rdsbliojj5d3othkq

An analytical model for on-chip interconnects in multimedia embedded systems

Yulei Wu, Geyong Min, Dakai Zhu, Laurence T. Yang
2013 ACM Transactions on Embedded Computing Systems  
Driven by the motivation of evaluating on-chip interconnects in multimedia embedded systems, a new analytical model is proposed to investigate the performance of the fat-tree based on-chip interconnection  ...  The traffic pattern has significant impact on the performance of network-on-chip. Many recent studies have shown that multimedia applications can be supported in on-chip interconnects.  ...  The lack of analytical performance models for such on-chip interconnects hinders efficient design for multimedia embedded systems.  ... 
doi:10.1145/2536747.2536751 fatcat:ddhwx7pllnc2lgmrhlrqix6qjy

GARNET: A detailed on-chip network model inside a full-system simulator

Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha
2009 2009 IEEE International Symposium on Performance Analysis of Systems and Software  
Acknowledgments The authors would like to thank the GEMS team at University of Wisconsin for helping with the integration of GAR- 41 NET. This work was supported by NSF (grant no.  ...  Base GARNET model design State-of-the-art on-chip interconnect: Modern state-of-theart on-chip network designs use a modular packet-switched fabric in which network channels are shared over multiple packet  ...  Validation of tornado traffic with ViChaR In [22] , results were presented for ViChaR for tornado traffic on a baseline network with the classic five-stage pipelined router.  ... 
doi:10.1109/ispass.2009.4919636 dblp:conf/ispass/AgarwalKPJ09 fatcat:gcumf767jnernguueoeg5jxixu

Performance evaluation and design tradeoffs of on-chip interconnect architectures

M. Bakhouya, S. Suboh, J. Gaber, T. El-Ghazawi, S. Niar
2011 Simulation modelling practice and theory  
Performance analysis and evaluation of on-chip interconnect architectures are widely based on simulations, which become computationally expensive, especially for large-scale NoCs.  ...  Network-on-Chip (NoC) has been proposed as an alternative to bus-based schemes to achieve high performance and scalability in System-on-Chip (SoC) design.  ...  A queuing-theory-based model for evaluating the average latency and energy consumption of on-chip interconnects was proposed in 21 .  ... 
doi:10.1016/j.simpat.2010.10.008 fatcat:dpwadk5mljdj5nggxtg5oknyce

Understanding the Impact of the Interconnection Network Performance of Multi-core Cluster Architectures

Norhazlina Hamid, Robert Walters, Gary Wills
2016 Journal of Computers  
This paper introduces simulation models of a new architecture for large-scale multi-core clusters to improve the communication performance within the interconnection network.  ...  Previous work on modelling either concentrated on inter-node communication network or focused on high performance multi-core architecture design without considering the effect of interconnection networks  ...  Acknowledgment The authors acknowledge the award of a Malaysia Fellowship Training scholarship (HLP), Public Service Department of Malaysia, to Norhazlina Hamid to allow this research to be undertaken.  ... 
doi:10.17706/jcp.11.2.132-139 fatcat:ldvs5gdcobdj7meooqphmznwfy

A design methodology for application-specific networks-on-chip

Jiang Xu, Wayne Wolf, Joerg Henkel, Srimat Chakradhar
2006 ACM Transactions on Embedded Computing Systems  
While a number of codesign methodologies have been proposed for on-chip computation subsystems, many works are needed for on-chip communication subsystems.  ...  to 2D mesh networks-on-chip.  ...  ACKNOWLEDGMENTS Authors would like to thank the reviewers and editors for their helpful comments.  ... 
doi:10.1145/1151074.1151076 fatcat:6xduw4pvwfh6zncpgqsjwxc5l4

A routerless system level interconnection network for 3D integrated systems

Kelli Ireland, Donald Chiarulli, Steven Levitan
2009 2009 IEEE International Conference on 3D System Integration  
This paper describes a new architectural paradigm for fully connected, single-hop system level interconnection networks.  ...  We present preliminary data from simulations of a network model and the design of a demonstration chip in stacked 3D integration technology.  ...  to unrealistic statistical methods for modeling traffic.  ... 
doi:10.1109/3dic.2009.5306557 dblp:conf/3dic/IrelandCL09 fatcat:b5lzksa7gjhdvfjnyehvdutqee

SpiNNaker

Javier Navaridas, Luis A. Plana, Jose Miguel-Alonso, Mikel Luján, Steve B. Furber
2010 Proceedings of the 7th ACM international conference on Computing frontiers - CF '10  
The SpiNNaker system is a biologically-inspired massively parallel architecture of bespoke multi-core System-on-Chips.  ...  The research question that we explore is the impact that spatial locality, temporal causality and burstiness of the traffic have on the performance of such interconnection network.  ...  Model of the System A detailed model of the SpiNNaker interconnection network is implemented in INSEE, a fast, flexible and mature simulation environment [17] for interconnection networks.  ... 
doi:10.1145/1787275.1787278 dblp:conf/cf/NavaridasPMLF10 fatcat:25v4oewj2regtgmhppdinontke

Implementation and Evaluation of On-Chip Network Architectures

Paul Gratz, Changkyu Kim, Robert McDonald, Stephen W. Keckler, Doug Burger
2006 Computer Design (ICCD '99), IEEE International Conference on  
A similar evolution is occurring in on-chip interconnect. This paper presents the design, implementation and evaluation of one such on-chip network, the TRIPS OCN.  ...  Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures.  ...  ACKNOWLEDGMENTS We thank the anonymous reviewers for their suggestions that helped improve the quality of this paper.  ... 
doi:10.1109/iccd.2006.4380859 dblp:conf/iccd/GratzKMKB06 fatcat:sre47d25qng47oyymfqi67zlbe

On-chip network resource management design and validation

Francesco Bruschi, Antonio Miele, Vincenzo Rana
2011 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation  
Designing interconnection networks for systems ona-chip is getting more complex due to the increasing number and heterogeneity of elements they connect, the variety of technologies adopted to transmit  ...  In this paper we consider the possibility of using MPSoC simulation frameworks for the early evaluation of reconfigurable networks-on-chip (NoCs), with the advantage of providing more realistic scenarios  ...  On the other hand Networks on Chip (NoCs), that are interconnection and on-chip systems that mimic the structure and functionalities of communication networks, are constantly gaining interest and importance  ... 
doi:10.1109/samos.2011.6045468 dblp:conf/samos/BruschiMR11 fatcat:ocrjlpe7kjdghkm6xu6r7teoqu

Effect of Application Mapping on Network-on-Chip Performance

Coskun Celik, Cuneyt F. Bazlamacci
2012 2012 20th Euromicro International Conference on Parallel, Distributed and Network-based Processing  
"A statistical traffic model for on-chip interconnection networks."  ...  for modeling self similarity;FBM is used in[11] for analyzing a network buffer under self similar traffic[11] I.  ...  A mapping instance and the routing protocol specify the aggregated traffic that enters to a buffer.  ... 
doi:10.1109/pdp.2012.48 dblp:conf/pdp/CelikB12 fatcat:pdprkj5zvfakxfi5zkkfyfoo2u

Automatic phase detection for stochastic on-chip traffic generation

Antoine Scherrer, Antoine Fraboulet, Tanguy Risset
2006 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06  
During System on Chip (SoC) design, Network on Chip (NoC) prototyping is used for adapting NoC parameters to the application running on the chip.  ...  We show that our traffic generators emulate precisely the behavior of processors and that our environment is a versatile tool for networks-on-chip prototyping.  ...  On-chip traffic modelling The traffic produced by a component is modelled as a sequence of transactions.  ... 
doi:10.1145/1176254.1176277 dblp:conf/codes/ScherrerFR06 fatcat:yyrrdrhofbd3ni4ybr4xmmiooq

Gpnocsim - A General Purpose Simulator for Network-On-Chip

Hemayet Hossain, Mostak Ahmed, Abdullah Al-Nayeem, Tanzima Zerin Islam, Md. Mostofa Akbar
2007 2007 International Conference on Information and Communication Technology  
Network-on-Chip (NoC) has gained considerable attention over the last few years as a paradigm for implementing communication among the system components embedded in a single chip.  ...  In this paper, we present gpNoCsim, a JAVA based general-purpose network simulator for NoC, which is built upon the object-oriented modular design of the NoC architecture components.  ...  Although the on-chip interconnection topologies have root in the interconnection architectures of high-performance parallel computing model, few of the interconnection architectures-for example, Mesh,  ... 
doi:10.1109/icict.2007.375388 fatcat:xcn2pusqavhwjght2kq7k2atbm

Dynamically reconfigurable simulation platform for 3D NoC based on multi-FPGA

Jintao Zheng, Ning Wu, Gaizhen Yan, Fen Ge, Lei Zhou
2015 IEICE Electronics Express  
Taking advantage of Three Dimension (3D) Integrated Circuit (IC) technology, 3D Network-on-Chip (NoC) is becoming a promising architecture of high-performance System-on-Chip (SoC).  ...  All the parameters can be dynamically reconfigured on-chip to model 3D NoC architecture without re-synthesizing.  ...  When the simulation time ends up, all the TRs will send the statistical figures to Traffic Analysis (TA), which is a global statistics module on the computer.  ... 
doi:10.1587/elex.12.20150065 fatcat:p57br4tf2fbyzbh3xyf2nkkx7i
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