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PT-Spike: A Precise-Time-Dependent Single Spike Neuromorphic Architecture with Efficient Supervised Learning [article]

Tao Liu, Lei Jiang, Yier Jin, Gang Quan, Wujie Wen
2018 arXiv   pre-print
In this work, a Precise-Time-Dependent Single Spike Neuromorphic Architecture, namely "PT-Spike", is developed to bridge this gap.  ...  efficiency and data processing capability of the time-based SNN at a more compact neural network model size when executing real cognitive tasks.  ...  A Precise-Time-Dependent Single Spike Neuromorphic Architecture, namely "PT-Spike", is proposed to facilitate the cognitive tasks like the MNIST digit recognition.  ... 
arXiv:1803.05109v1 fatcat:tuve33w7zbaflcudfav7geh75a

FPT-spike: a flexible precise-time-dependent single-spike neuromorphic computing architecture

Tao Liu, Gang Quan, Wujie Wen
2020 CCF Transactions on High Performance Computing  
In this work, we make an early attempt to fill this gap: that said, a flexible precisetime-dependent single-spike neuromorphic computing architecture, namely "FPT-Spike", is developed.  ...  For SNNs, a large body of prior work were conducted on the spiking system design with a focus on using the spike firing rate (or rate-coded) for fulfilling the practical cognitive tasks.  ...  We hope our study can inspire and motivate more in-depth research on the time-based SNN for realistic applications in energy-constraint platforms.  ... 
doi:10.1007/s42514-020-00037-6 fatcat:2hevpn5brfealictsg2vupzc6i

MT-Spike: A Multilayer Time-based Spiking Neuromorphic Architecture with Temporal Error Backpropagation [article]

Tao Liu, Zihao Liu, Fuhong Lin, Yier Jin, Gang Quan, Wujie Wen
2018 arXiv   pre-print
In this work, a practical multilayer time-based spiking neuromorphic architecture, namely "MT-Spike", is developed to fill this gap.  ...  Time-based spiking neural network has recently emerged as a promising solution in Neuromorphic Computing System designs for achieving remarkable computing and power efficiency within a single chip.  ...  In this work, we propose a multilayer time-based spiking neuromorphic architecture, namely "MT-Spike".  ... 
arXiv:1803.05117v1 fatcat:6jlqjso3gfc6pno5scr53uzxeu

A hybrid analog/digital Spike-Timing Dependent Plasticity learning circuit for neuromorphic VLSI multi-neuron architectures

Hesham Mostafa, Federico Corradi, Fabio Stefanini, Giacomo Indiveri
2014 2014 IEEE International Symposium on Circuits and Systems (ISCAS)  
In this paper we present an analog/digital Spike-Timing Dependent Plasticity (STDP) circuit that changes its internal state in a continuous analog way on short biologically plausible time scales and drives  ...  its weight to one of two possible bi-stable states on long time scales.  ...  pre − t post spike times.  ... 
doi:10.1109/iscas.2014.6865270 dblp:conf/iscas/MostafaCSI14 fatcat:gz4jvzjj2ngungmq27g3kg523a

Architecture and Design of a Spiking Neuron Processor Core Towards the Design of a Large-scale Event-Driven 3D-NoC-based Neuromorphic Processor

Mark Ogbodo, Khanh Dang, Fukuchi Tomohide, Abderazek Abdallah, D. Roy
2020 SHS Web of Conferences  
Neuromorphic computing tries to model in hardware the biological brain which is adept at operating in a rapid, real-time, parallel, low power, adaptive and fault-tolerant manner within a volume of 2 liters  ...  This paper presents a spiking neuron processor core suitable for an event-driven Three-Dimensional Network on Chip (3D-NoC) SNN based neuromorphic systems.  ...  Neuromorphic architectures take advantage of the sparsity of spikes in SNN to reduce power consumption by power gating parts of the network that are not receiving spikes at any point in time.  ... 
doi:10.1051/shsconf/20207704003 fatcat:hdhnbsz3ovc6rgkn57cxz5qlby

Impact of increasing number of neurons on performance of neuromorphic architecture

Mahyar Shahsavari, Pierre Boulet, Asadollah Shahbahrami, Said Hamdioui
2017 2017 19th International Symposium on Computer Architecture and Digital Systems (CADS)  
The spike neural networks inspired from physiological brain architecture, is a neuromorphic hardware implementation of network of neurons.  ...  A sample of neuromorphic architecture has two layers of neurons, input and output. The number of input neurons is fixed based on the input data patterns.  ...  ACKNOWLEDGMENTS This work has been supported by European Network on High Performance and Embedded Architecture and Compilation (HiPEAC) in collaboration grant agreement H2020-687698.  ... 
doi:10.1109/cads.2017.8310732 fatcat:a2g5v4kx4rhsjemhq6d2rmjctq

On the Role of System Software in Energy Management of Neuromorphic Computing [article]

Twisha Titirsha, Shihao Song, Adarsha Balaji, Anup Das
2021 arXiv   pre-print
In this work, we formulate the energy consumption of a neuromorphic hardware, considering the power consumed by neurons and synapses, and the energy consumed in communicating spikes on the interconnect  ...  that are implemented using Spiking Neural Network (SNN).  ...  Placement of the SNN to a mesh architecture.. Figure 7 . 7 Example of calculation for a clustered SNN placed on a mesh architecture.  ... 
arXiv:2103.12231v1 fatcat:ltcroj7vynh4db55m6tzwmtm4y

Run-time Mapping of Spiking Neural Networks to Neuromorphic Hardware [article]

Adarsha Balaji and Thibaut Marty and Anup Das and Francky Catthoor
2020 arXiv   pre-print
In this paper, we propose a design methodology to partition and map the neurons and synapses of online learning SNN-based applications to neuromorphic architectures at run-time.  ...  , and step 2 is a hill-climbing optimization algorithm that minimizes the total spikes communicated between clusters, improving energy consumption on the shared interconnect of the architecture.  ...  In this paper, we propose a design methodology to partition and map the neurons and synapses of online learning SNN-based applications to neuromorphic architectures at run-time.  ... 
arXiv:2006.06777v1 fatcat:bwncem4t55fq3eugwzg2mxawz4

Integer Factorization with a Neuromorphic Sieve [article]

John V. Monaco, Manuel M. Vindiola
2018 arXiv   pre-print
This work presents a neuromorphic sieve that achieves a constant time check for smoothness by exploiting two characteristic properties of neuromorphic architectures: constant time synaptic integration  ...  On a von Neumann architecture, sieving has log-log amortized time complexity to check each value for smoothness.  ...  TrueNorth is a pipelined architecture, and the postsynaptic spikes from the tonic spiking neurons at time t are received by the smoothness neuron at time t+2.  ... 
arXiv:1703.03768v2 fatcat:naon6x4md5gc7dud77ck2l4g7e

Mapping of local and global synapses on spiking neuromorphic hardware

Anup Das, Yuefeng Wu, Khanh Huynh, Francesco Dell'Anna, Francky Catthoor, Siebren Schaafsma
2018 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
Our framework is implemented in Python, interfacing CARLsim, a GPU-accelerated application-level spiking neural network simulator with an extended version of Noxim, for simulating time-multiplexed interconnects  ...  Using power numbers from in-house neuromorphic chips, we demonstrate significant reductions in energy consumption and spike latency over PACMAN, the widely-used partitioning technique for SNNs on SpiNNaker  ...  Run-time SNN mapping will be addressed in future. Figure 1 1 shows the general architecture of a modern neuromorphic hardware.  ... 
doi:10.23919/date.2018.8342201 dblp:conf/date/0001WHDCS18 fatcat:66xqcf5qtng7dckw4tgpr2rwmy

Forward table-based presynaptic event-triggered spike-timing-dependent plasticity

Bruno U. Pedroni, Sadique Sheik, Siddharth Joshi, Georgios Detorakis, Somnath Paul, Charles Augustine, Emre Neftci, Gert Cauwenberghs
2016 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS)  
Spike-timing-dependent plasticity (STDP) incurs both causal and acausal synaptic weight updates, for negative and positive time differences between pre-synaptic and postsynaptic spike events.  ...  For realizing such updates in neuromorphic hardware, current implementations either require forward and reverse lookup access to the synaptic connectivity table, or rely on memory-intensive architectures  ...  SPIKE-TIMING DEPENDENT PLASTICITY WITHOUT REVERSE CONNECTIVITY TABLE LOOKUP A fundamental aspect of the crossbar and index-based architectures for STDP is that a core has information about the pre-synaptic  ... 
doi:10.1109/biocas.2016.7833861 dblp:conf/biocas/PedroniSJDPANC16 fatcat:uivbibzyzvh3xh7gtutfjyntb4

Forward Table-Based Presynaptic Event-Triggered Spike-Timing-Dependent Plasticity [article]

Bruno U. Pedroni, Sadique Sheik, Siddharth Joshi, Georgios Detorakis, Somnath Paul, Charles Augustine, Emre Neftci, Gert Cauwenberghs
2016 arXiv   pre-print
Spike-timing-dependent plasticity (STDP) incurs both causal and acausal synaptic weight updates, for negative and positive time differences between pre-synaptic and post-synaptic spike events.  ...  For realizing such updates in neuromorphic hardware, current implementations either require forward and reverse lookup access to the synaptic connectivity table, or rely on memory-intensive architectures  ...  SPIKE-TIMING DEPENDENT PLASTICITY WITHOUT REVERSE CONNECTIVITY TABLE LOOKUP A fundamental aspect of the crossbar and index-based architectures for STDP is that a core has information about the pre-synaptic  ... 
arXiv:1607.03070v2 fatcat:5nk2h52c6ngixf5cvkvaopp6ym

Adaptive motor control and learning in a spiking neural network realised on a mixed-signal neuromorphic processor [article]

Sebastian Glatz, Julien N.P. Martel, Raphaela Kreiser, Ning Qiao, and Yulia Sandamirskaya
2018 arXiv   pre-print
The prototype neuromorphic device that features 256 spiking neurons allows us to realise a simple proof of concept architecture for the purely neuromorphic motor control and learning.  ...  The architecture can be easily scaled-up if a larger neuromorphic device is available.  ...  Such online learning in a neuromorphic device has been demonstrated for the first time here. Fig. 3(a) shows the output of the neuromorphic chip (spikes over time) in a sequence of control tasks.  ... 
arXiv:1810.10801v1 fatcat:lgscximbrnampn5okdqeb5y5lm

Classification of multivariate data with a spiking neural network on neuromorphic hardware

Michael Schmuker, Thomas Pfeil, Martin P Nawrot
2013 BMC Neuroscience  
At the same time neuromorphic hardware systems have evolved to a state where fast in silico implementations of complex neural networks are feasible.  ...  Our classifier network is an important proof-of-principle for a bio-inspired functional spiking network implemented on neuromorphic hardware performing a real-world computing task.  ...  At the same time neuromorphic hardware systems have evolved to a state where fast in silico implementations of complex neural networks are feasible.  ... 
doi:10.1186/1471-2202-14-s1-p290 fatcat:vqf2pe5wongw3dq3jxb57ymihy

The impact of on-chip communication on memory technologies for neuromorphic systems

Saber Moradi, Rajit Manohar
2018 Journal of Physics D: Applied Physics  
Emergent nanoscale non-volatile memory technologies with high integration density offer a promising solution to overcome the scalability limitations of CMOS-based neural networks architectures, by efficiently  ...  In this paper, we elaborate on the communication requirements of large-scale neuromorphic designs, and point out the differences with the conventional network-on-chip architectures.  ...  Since neuromorphic systems represent information in the timing of spikes, it is important that the communication network preserve the delivery time of a spike relative to the time it was generated.  ... 
doi:10.1088/1361-6463/aae641 fatcat:kw6alqj6grdlpddvrtocenxwfm
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