Filters








11,209 Hits in 8.8 sec

A Small, Fast and Low-Power Register File by Bit-Partitioning

M. Kondo, H. Nakamura
11th International Symposium on High-Performance Computer Architecture  
However, a larger register file causes longer access delays and more power consumption.  ...  Thus, we propose to use of these useless upper bits for other operands by partitioning the register entries.  ...  This work is partly supported by the Ministry of Education, Culture, Sports, Science and Technology, Grant-in-Aid (No. 14380136).  ... 
doi:10.1109/hpca.2005.3 dblp:conf/hpca/KondoN05 fatcat:euwwu6p2zjaltcawhrodry64g4

Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor

R.A. Ravindran, R.M. Senger, E.D. Marsman, G.S. Dasika, M.R. Guthaus, S.A. Mahlke, R.B. Brown
2005 IEEE transactions on computers  
Low-power embedded processors utilize compact instruction encodings to achieve small code size.  ...  To support the windowed register file, we designed and implemented a graph partitioning-based compiler algorithm that partitions program variables and temporaries referenced within a procedure across multiple  ...  Digital cell libraries and SRAMs were supplied by Artisan Components, Inc.  ... 
doi:10.1109/tc.2005.132 fatcat:ow4igm53l5h45lyj3osm7thrma

Asymmetrically Banked Value-Aware Register Files

Shuai Wang, Hongyan Yang, Jie Hu, Sotirios G. Ziavras
2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)  
In this paper, we propose a new microarchitecture, the asymmetrically-banked value-aware register file (AB-VARF), to exploit the prevailing narrowwidth register values for low-latency and power-efficient  ...  Designing high-performance low-power register files is of critical importance to the continuation of current performance advances in wide-issue and deeply-pipelined superscalar microprocessors.  ...  from) small and low-power narrow-width banks.  ... 
doi:10.1109/isvlsi.2007.27 dblp:conf/isvlsi/WangYHZ07 fatcat:ci3tppztv5febp6onhwskq2odu

Exploiting narrow-width values for thermal-aware register file designs

Shuai Wang, Jie Hu, S.G. Ziavras, Sung Woo Chung
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
In this paper, we perform a detailed study on the thermal behavior of a low-power value-aware register file (VARF) that is subjected to internal fine-grain hotspots.  ...  The experimental results show that the ID-VARF can improve the performance by 26.1% and 7.2% over the conventional register file and the original VARF design, respectively.  ...  The left half of the register file is gated by the flag bit for power savings.  ... 
doi:10.1109/date.2009.5090887 dblp:conf/date/WangHZC09 fatcat:gscr7dinmvel5bjqiyngyhvhpa

Asymmetrically banked value-aware register files for low-energy and high-performance

Shuai Wang, Hongyan Yang, Jie Hu, Sotirios G. Ziavras
2008 Microprocessors and microsystems  
In this paper, we propose a new microarchitecture, the asymmetrically banked value-aware register file (AB-VARF), to exploit the prevailing narrow-width register values for low-latency and energy-efficient  ...  Our experimental evaluation with SPEC CINT2000 benchmark suite shows that AB-VARF reduces the energy consumption by 78.4% over a conventional register file, on the average, at the cost of a 0.7% performance  ...  from) the small and low-energy narrow-width banks.  ... 
doi:10.1016/j.micpro.2007.10.004 fatcat:rw6allqxtrduzfqvh4yblqgune

The energy complexity of register files

V. Zyuban, P. Kogge
1998 Proceedings of the 1998 international symposium on Low power electronics and design - ISLPED '98  
Register files (RF) represent a substantial portion of the energy budget in modern processors, and are growing rapidly with the trend towards wider instruction issue.  ...  However, as this paper shows, it appears that none of these will be enough to prevent centralized register files from becoming the dominant power component of next-generation superscalar computers, and  ...  If this is the case, then we can implement a CPU as a collection of processing unit clusters and provide each cluster with a local physical register file which will be small, fast and low-power.  ... 
doi:10.1145/280756.280943 dblp:conf/islped/ZyubanK98 fatcat:qglxk5euhzgvdbnwbrdup4brai

Enhanced Duplication: a Technique to Correct Soft Errors in Narrow Values

I. Burak Karsli, Pedro Reviriego, M. Fatih Balli, Oguz Ergin, J. A. Maestro
2013 IEEE computer architecture letters  
Soft errors are transient errors that can alter the logic value of a register bit causing data corruption. They can be caused by radiation particles such as neutrons or alpha particles.  ...  These techniques replicate the narrow value over the unused register bits such that errors can be detected when the value is duplicated and corrected when the value is tripled.  ...  ACKNOWLEDGEMENTS This work was supported in part by the Spanish Ministry of Science and Education under Grant AYA2009-13300-C03 and by the Scientific and Technological Research Council of Turkey (TUBITAK  ... 
doi:10.1109/l-ca.2012.6 fatcat:qf7vnvgixbfyzcazstxw2nkvxu

Soft error vulnerability aware process variation mitigation

Xin Fu, Tao Li, Jose A. B. Fortes
2009 2009 IEEE 15th International Symposium on High Performance Computer Architecture  
It tolerates the deleterious impact of variable latency techniques on soft error reliability by reducing the quantity and residency cycle of vulnerable bits in the microarchitecture structure at a fine  ...  Prior studies have shown that chip operating frequency and leakage power can have large variations due to fluctuations in transistor gate length and sub-threshold voltage.  ...  Multi-core Computing Awards and by three IBM Faculty Awards.  ... 
doi:10.1109/hpca.2009.4798241 dblp:conf/hpca/FuLF09 fatcat:ghsflmtfv5ajbausi567pqf6be

CRIB

Erika Gunadi, Mikko H. Lipasti
2011 Proceeding of the 38th annual international symposium on Computer architecture - ISCA '11  
We propose CRIB: Consolidated Rename, Issue, and Bypass as a solution to the power problem. Using CRIB, out-of-order execution is done without explicit register renaming.  ...  By removing explicit register renaming, several supporting structure needed for operand delivery can be eliminated. Hence, power consumption related to operand delivery can be dramatically reduced.  ...  A large multiported physical register file is replaced by a small spatially-organized architected register file which consists of a simple rank of latches.  ... 
doi:10.1145/2000064.2000068 dblp:conf/isca/GunadiL11 fatcat:4eghzwmddnedbh7nvkezgi422u

Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors

Kiran Puttaswamy, Gabriel H. Loh
2007 2007 IEEE 13th International Symposium on High Performance Computer Architecture  
reducing total power by 20% (min 15%, max 30%).  ...  Our 3D/thermal-aware microarchitecture contributions include a significance-partitioned datapath that places the frequently switching 16-bits on the top die, a 3D-aware instruction scheduler allocation  ...  Acknowledgments Funding and equipment for this project have been provided by Intel Corporation and a grant from the Microelectronics Advanced Research Corporation (MARCO).  ... 
doi:10.1109/hpca.2007.346197 dblp:conf/hpca/PuttaswamyL07 fatcat:rztjintxqfaebbw3q6zy5strku

Low power aging-aware register file design by duty cycle balancing

Shuai Wang, Tao Jin, Chuanlei Zheng, Guangshan Duan
2012 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
By gating the leading bits of the narrow-width values during the register accesses, our AARF can also achieve a significantly power reduction, which will further reduce the temperature and NBTI degradation  ...  The proposed AARF design can mitigate the negative aging effects by balancing the duty cycle ratio of the internal bits in register files.  ...  ACKNOWLEDGMENT This work was supported in part by a grant from Chinese NSF Award 61100035.  ... 
doi:10.1109/date.2012.6176528 dblp:conf/date/WangJZD12 fatcat:blesvxbzrfgb5gssgftobzxtd4

Energy-Efficient Design of the Reorder Buffer [chapter]

Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
2002 Lecture Notes in Computer Science  
These techniques are: 1) dynamic ROB resizing; 2) the use of low-power comparators that dissipate energy mainly on a full match of the comparands and, 3) the use of zero-byte encoding.  ...  We validate our results by executing the complete suite of SPEC 95 benchmarks on a true cycle-by-cycle hardware-level simulator and using SPICE measurements for actual layouts of the ROB in 0.5 micron  ...  Second, we propose the use of fast low-power Appears in the Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation, September, 2002 comparators, as introduced  ... 
doi:10.1007/3-540-45716-x_29 fatcat:242nzaheyrcmbccys2xvsghvuq

CRIB

Erika Gunadi, Mikko H. Lipasti
2011 SIGARCH Computer Architecture News  
the need for a multiported register file, instead storing architected state in a simple rank of latches.  ...  Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined execution lanes.  ...  ACKNOWLEDGEMENTS This work was supported in part by NSF award CCF-0702272, financial support from IBM, and equipment donations from HP.  ... 
doi:10.1145/2024723.2000068 fatcat:5jrz47rv6ngxplvufmp7wrqkeu

A high state of modular transistor on a 105 kW HVPS for X-rays tomography Applications

2019 Sukkur IBA journal of emerging technologies  
This technique is so fast and less costly than the previous technique. In this paper, such type of high voltage input power supply (HVPS) technique is used.  ...  X-rays tomography work for the production of enhanced imaging at low radiation rate.  ...  Bit-partitioned Register File (BPRF) considered their designing mechanism from basic cache organization mechanism. It is designed based on a conventional dynamically scheduled superscalar processor.  ... 
doi:10.30537/sjet.v2i2.475 fatcat:udzzdj5yu5ddfhynm3l4gzxpvu

High-Performance Data Compression-Based Design for Dynamic IoT Security Systems

Maha Aboelmaged, Ali Shisha, Mohamed A. Abd El Ghany
2021 Electronics  
The proposed design seeks to reduce the FPGA reconfiguration time by the application of LZ4 (Lempel-Ziv4) compression and decompression techniques on the ciphers' bitstream files.  ...  IoT technology is evolving at a quick pace and is becoming an important part of everyday life.  ...  The reconfiguration of the FPGA functions by changing the partial bit file in Reconfig Block "A" by one of the bit files (A1.bit, A2.bit, A3.bit, A4.bit) where the selection of the bit files depends on  ... 
doi:10.3390/electronics10161989 fatcat:j3f7karmmzhrhcaopc5vglgdfe
« Previous Showing results 1 — 15 out of 11,209 results