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A single chip low power asynchronous implementation of an FFT algorithm for space applications

B.W. Hunt, K.S. Stevens, B.W. Suter, D.S. Gelosh
Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems  
A fully asynchronous xed p oint FFT processor is introduced for low power space applications.  ...  The architecture i s b ased on an algorithm developed by Suter and Stevens speci cally for a low power implementation.  ...  E a c h h a s contributed direct support on this project or provided the groundwork for it to begin.  ... 
doi:10.1109/async.1998.666507 dblp:conf/async/HuntSSG98 fatcat:tlfjydpvy5horn4kwxkc4fgipu

Implementation of a Fast Fourier transform algorithm onto a manycore processor

Julien Hascoet, Jean-Francois Nezan, Andrew Ensor, Benoit Dupont de Dinechin
2015 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP)  
This enables to use only two first-generation MPPA chips per flow of data coming from the receivers, for a total power consumption of 17.4W.  ...  We address this challenge by optimizing a FFT implementation for execution on the Kalray MPPA manycore processor.  ...  This SoC is widely used for its low power capabilities to implement signal and image processing applications [10] .  ... 
doi:10.1109/dasip.2015.7367270 dblp:conf/dasip/HascoetNED15 fatcat:sx3trc2vwnbrfiklhzp6ooil6i

On The Design And Fpga Implementation Of Real-Time Scanned-Array 2D Frequency-Planar Beam Filters

Arjuna Madanayake, Leonard Bruton
2004 Zenodo  
Publication in the conference proceedings of EUSIPCO, Viena, Austria, 2004  ...  For single-chip single-A/D 2D filter implementations, we propose the following straightforward asynchronous A/D TDM strategy and we consider its effect on the design and implementation of single-chip 2D  ...  From Algorithm 1, we show that a signal component shifted by a single spatial location is equivalent to a temporal delay of AS T ∆ for the scanned sig- .  ... 
doi:10.5281/zenodo.38223 fatcat:n46p4ccmfncfbopq4wdlhr642e

Design and Application Space Exploration of a Domain-Specific Accelerator System

Fan Feng, Li Li, Kun Wang, Yuxiang Fu, Guoqiang He, Hongbing Pan
2018 Electronics  
This paper describes a radar signal processing oriented configurable accelerator and the application space exploration of the system.  ...  The experimental results show that for different algorithms, the proposed system achieves 1.9× to 10.1× performance gain compared with a state-of-the-art TI DSP chip.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/electronics7040045 fatcat:jolibhbekfeihlyzqwzke6kyka

Fast Fourier Transform Implementation on FPGA Using Soft-Core Processor NIOS II

Poonam S. Isasare, Mahesh T. Kolte
2014 International Journal of Engineering Trends and Technoloy  
This methodology saves lot of time required for implementation and validation of the complex design. In this work we present a preliminary performance evaluation of the C2H compiler on FFT algorithm.  ...  In this work we use of the C2H Altera compiler for the automatic VHDL synthesis of FFT algorithm.  ...  A naïve (non-FFT) implementation of an n-point DFT requires n2 complex multiplications. These are some basic facts about the FFT algorithm to be aware of:  The FFT operates on complex data.  ... 
doi:10.14445/22315381/ijett-v10p278 fatcat:zulehnxfqfcqllrwnojgmeapvy

High-Performance DSP Processors for Intelligence Applications

Vinni Sharma
Fast multiply/ accumulate time, integrated on-chip random access memory (RAM), large address space, high precision and multiprocessor support are necessary for efficient virtual implementation of neural  ...  DSPs provide high computing power by employing a high level of on-chip parallelism, integrated hardware multipliers, carefully tailored instruction sets, memory organization schemes, hardware support for  ...  The application area of early single-chip general-purpose DSPs was primarily in digital filter implementation.  ... 
doi:10.17148/ijireeice.2015.3732 fatcat:gck3ih7evzhfbjg6wpkft47jsi

On the single-chip implementation of a Hiperlan/2 and IEEE 802.11a capable modem

E. Grass, K. Tittelbach-Helmrich, U. Jagdhold, A. Troya, G. Lippert, O. Kruger, J. Lehmann, K. Maharatna, K.F. Dombrowski, N. Fiebig, R. Kraemer, P. Mahonen
2001 IEEE personal communications  
single chip.  ...  Low cost and low power dissipation will be a prerequisite for most mobile applications. One way to realize low-cost systems is to reduce the system complexity and deploy highly integrated components.  ...  The single-chip wireless broadband modem is part of an initiative for a truly single-chip PDA that additionally consists of an application engine, a protocol processor, and a power management and test  ... 
doi:10.1109/98.972168 fatcat:l4yy3s7klvanfphfwtix54nq5a

Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach

Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani (+9 others)
2010 2010 IEEE Computer Society Annual Symposium on VLSI  
The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption  ...  MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure; 2  ...  From the set of core models in the design space, the approach finds the most optimal for the given algorithm. 520 E.  ... 
doi:10.1109/isvlsi.2010.71 dblp:conf/isvlsi/CandaeleASAXBBSLCCHJVKTIKWVM10 fatcat:43mxty533vcnnp25k5vjmrpey4

A 10-pJ/instruction, 4-MIPS micropower DSP for sensor applications

Nathan Ickes, Daniel Finchelstein, Anantha P. Chandrakasan
2008 2008 IEEE Asian Solid-State Circuits Conference  
ACKNOWLEDGMENTS The authors would like to thank STMicroelectronics for chip fabrication.  ...  This work was funded in part by DARPA, Texas Instruments, and the Interconnect Focus Center, one of ve research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation  ...  The accelerator consists of a register le holding up to eight 16-bit tap coef cients, a 16 16 circular buffer for holding the input samples, a single multiplyaccumulate unit, an adder/subtracter, and a  ... 
doi:10.1109/asscc.2008.4708784 fatcat:xtz3j22bifacholh5fpdlwqog4

FFTW and Complex Ambiguity Function performance on the Maestro processor

Karandeep Singh, John Paul Walters, Joel Hestness, Jinwoo Suh, Craig M. Rogers, Stephen P. Crago
2011 2011 Aerospace Conference  
Maestro is a 49-core general-purpose, radiationhardened processor for space. Fourier Transform is an important computation in many space applications.  ...  We ported FFTW library to the Maestro processor and used it extensively in implementing the Complex Ambiguity Function (CAF), which is a reference space application.  ...  DFTs are very commonly used computation in many space applications, so a good implementation of this very important function is necessary for low power, high performance requirements in this domain.  ... 
doi:10.1109/aero.2011.5747455 fatcat:ey5htjrb5fehzfg4fb5xet2ifq

Exploration of distributed shared memory architectures for NoC-based multiprocessors

Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
2007 Journal of systems architecture  
In this paper, a distributed shared memory architecture has been explored, that is suitable for low-power on-chip multiprocessors based on NoC.  ...  Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications.  ...  For this purpose, a distributed shared memory architecture has been proposed, that is suitable for low-power on-chip multiprocessors and supported by an on-chip hardware MMU.  ... 
doi:10.1016/j.sysarc.2007.01.008 fatcat:6jjvd42x2vetdmai3ftipxlg5e

Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors

Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
2006 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation  
In this paper, a distributed shared memory architecture has been explored, that is suitable for low-power on-chip multiprocessors based on NoC.  ...  Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications.  ...  For this purpose, a distributed shared memory architecture has been proposed, that is suitable for low-power on-chip multiprocessors and supported by an on-chip hardware MMU.  ... 
doi:10.1109/icsamos.2006.300821 dblp:conf/samos/MonchieroPSV06 fatcat:cu6537637na4vgk3bfthdjxuoe

A 64-Point Fourier Transform Chip for High-Speed Wireless LAN Application Using OFDM

K. Maharatna, E. Grass, U. Jagdhold
2004 IEEE Journal of Solid-State Circuits  
In this paper, we present a novel fixed-point 16-bit word-width 64-point FFT/IFFT processor developed primarily for the application in an OFDM-based IEEE 802.11a wireless LAN baseband processor.  ...  These features show that though it has been developed primarily for application in the IEEE 802.11a standard, it can be used for any application that requires fast operation as well as low power consumption  ...  A new low-power high-performance 64-point FFT/IFFT chip for WLAN applications has been successfully designed and fabricated based on the architecture described.  ... 
doi:10.1109/jssc.2003.822776 fatcat:uo7ibrhhuvhfne36wyfnza4iri

24.3 An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis

Dongsuk Jeon, Yen-Po Chen, Yoonmyung Lee, Yejoong Kim, Zhiyoong Foo, Grant Kruger, Hakan Oral, Omer Berenfeld, Zhengya Zhang, David Blaauw, Dennis Sylvester
2014 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)  
Electrocardiography (ECG) is a critical source of information for a number of heart disorders.  ...  As in other implantable systems, low power consumption is a critical factor; in this case to provide a sufficiently long operating time between wireless recharge events.  ...  Traditional asynchronous logic uses dynamic logic, which suffers from high leakage in a low voltage/frequency ECG application.  ... 
doi:10.1109/isscc.2014.6757494 dblp:conf/isscc/JeonCLKFKOBZBS14 fatcat:iqi37yamyzg4bo4n5j7zgvtlfa

Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example

Chia-Hsiang Yang, Tsung-Han Yu, Dejan Markovic
2012 IEEE Journal of Solid-State Circuits  
As a proof of concept, a 128-to 2048-point FFT processor for 3GPP-LTE standard has been implemented in a 65-nm CMOS process.  ...  This paper presents a design methodology for power and area minimization of flexible FFT processors.  ...  For example, a split-radix FFT with minimal multiplicative complexity is proposed in [18] . High-speed low-power hardware implementations are presented in [19] , [20] .  ... 
doi:10.1109/jssc.2011.2176163 fatcat:76aye5ujynbwnozbwbvvpptkxm
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