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Architectural Implications of Cache Coherence Protocols with Network Applications on Chip MultiProcessors [chapter]

Kyueun Yi, Jean-Luc Gaudiot
2007 Lecture Notes in Computer Science  
We investigate the architectural implications of cache coherence protocols with network workloads on CMPs.  ...  Our results show that the token protocol which uses the tokens to control read/write permission of shared data blocks shows better performance than the directory protocol by a factor of 13.4%.  ...  There are 4 kinds of the options for CMP implementation [14] , a conventional microprocessor, a simple chip multiprocessor, a shared-cache chip multiprocessor, and a multithreaded, shared-cache chip multiprocessor  ... 
doi:10.1007/978-3-540-74784-0_40 fatcat:fw6km2m6vvfalnszobexoca2xe

Integrating cache coherence protocols for heterogeneous multiprocessor systems. 1

T. Suh, H.-H.S. Lee, D.M. Blough
2004 IEEE Micro  
THIS SYSTEMATIC METHODOLOGY MAINTAINS CACHE COHERENCY INA HETEROGENEOUS SHARED-MEMORY MULTIPROCESSOR SYSTEM ON A CHIP.  ...  ) on a bus as explained in a later section on region-based cache coherence.  ... 
doi:10.1109/mm.2004.33 fatcat:ltfbpcs4dzd3noxh4443pv7tn4

Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture [chapter]

Francisco J. Villa, Manuel E. Acacio, José M. García
2005 Lecture Notes in Computer Science  
The characterization is performed making use of a new simulator that we have called DCMPSIM and extends the Rice Simulator for ILP Multiprocessors (RSIM) with the functionality required to model a contemporary  ...  are and, thus, where computer architects have to place special emphasis to improve the performance of future dense single-chip multiprocessors, which will integrate 16 or more processor cores.  ...  Acknowledgments This work has been supported by the Spanish Ministry of Ciencia y Tecnología and the European Union (Feder Funds) under grant TIC2003-08154-C06-03.  ... 
doi:10.1007/11557654_27 fatcat:lzly4lmavnblpmd763xay5lfva

On the Evaluation of Dense Chip-Multiprocessor Architectures

Francisco Villa, Manuel Acacio, Jose Garcia
2006 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation  
The Shared Bus Fabric architecture (SBF) features a snoop cache-coherence protocol and is based on a high-performance bus fabric interconnection network.  ...  In this paper we present an exhaustive performance evaluation of two recently proposed D-CMP architectures, making special emphasis on the solution to the cache-coherence problem that each one of them  ...  ACKNOWLEDGMENTS This work has been supported by the Spanish Ministry of Educación y Ciencia and the European Union (Feder Funds) under grant TIC2003-08154-C06-03.  ... 
doi:10.1109/icsamos.2006.300804 dblp:conf/samos/VillaAG06 fatcat:a6weuaezpvcxlabl4bywfhhexy

Shared Memory Multiprocessors [chapter]

2004 Parallel Computing on Heterogeneous Networks  
For example, in the dual-core Itanium 2 Montecito processor (Figure 2 ), every core has 3 levels of private on-chip cache connected to a shared off-chip memory controller.  ...  Therefore, cache coherence controller is usually inserted between the memory bus and the L2 cache, so cache coherence is enforced across L2 caches.  ... 
doi:10.1002/0471654167.ch3 fatcat:dvaj7kmetfgr7bkmdrmvzljwda

The Scalable Coherent Interface and related standards projects

D.B. Gustavson
1992 IEEE Micro  
The SCI protocols support cache coherence in a distributed-shared-memory multiprocessor model, message passing, I/O, and local-area-network-like communication over fiber optic or wire links.  ...  (about 0.25 V) differential signals suitable for low power interfaces for CMOS or GaAs VLSI implementations of SCI; P1596.4 defines a high performance memory chip interface using these signals; P1596.5  ...  Using multiple buses to get more than one transfer at a time results in a complex (expensive) bus-bridge mechanism to maintain cache consistency (coherence) in shared-memory systems that use bus-snooping  ... 
doi:10.1109/40.124376 fatcat:3a4opujvrvdllm3aag3cgo6o6a

Cache Coherence Protocols in Distrubted Systems

Hanan Shukur, Subhi Zeebaree, Rizgar Zebari, Omar Ahmed, Lailan Haji, Dildar Abdulqader
2020 Journal of Applied Science and Technology Trends  
Also, cache coherent protocols have a great task for keeping the interconnection of caches in a multiprocessor environment.  ...  Moreover, the overall performance of distributed shared memory multiprocessor system is influenced by the used cache coherence protocol type.  ...  Wang and D. Wang [37] proposed a model for network on chip based energy used for cache coherence protocol.  ... 
doi:10.38094/jastt1329 fatcat:si6jqibdnbfufnthjsyq5gmpre

Design of a bus-based shared-memory multiprocessor DICE

Gyungho Lee, Bland W Quattlebaum, Sangyeun Cho, Larry L Kinney
1999 Microprocessors and microsystems  
DICE tries to optimize COMA for a shared-bus medium, in particular to reduce detrimental effects of the cache coherence and the 'last memory block' problem on replacement.  ...  DICE is a shared-bus multiprocessor based on a distributed shared-memory architecture, known as cache-only memory architecture (COMA).  ...  Manu Agarwal, Sujat Jamil and Jinseok Kong contributed to the project on which this work is based. An earlier version of the paper was presented in Ref. [26] .  ... 
doi:10.1016/s0141-9331(98)00097-0 fatcat:gmluftwjg5g3ximidir4rq3b7y

Design and implementation of the NUMAchine multiprocessor

A. Grbic, M. Stumm, Z. Vranesic, Z. Zilic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless, N. Manjikian, S. Srbljic
1998 Proceedings of the 35th annual conference on Design automation conference - DAC '98  
As the market for CC-NUMA multiprocessors expands, this research project provides a timely architectural design and cost-effective prototype.  ...  This paper describes the design and implementation of the NUMAchine multiprocessor.  ...  This type of multiprocessor is known as a CC-NUMA (Cache-Coherent Non-Uniform Memory Access) distributed shared-memory multiprocessor.  ... 
doi:10.1145/277044.277057 dblp:conf/dac/GrbicBCGGLLMSSVZ98 fatcat:zku2cnlt55cp5nshogbyxiqsly

Importance of Coherence Protocols with Network Applications on Multicore Processors

Kyueun Yi, Won W. Ro, Jean-Luc Gaudiot
2013 IEEE transactions on computers  
In this paper, we focus on the cache coherence protocols which are central to the design of multicore-based network processors.  ...  With an 8-core configuration, token protocols improves the performance compared to directory protocols by a factor of nearly 4 on average.  ...  Fig. 1a shows a conventional microprocessor, Fig. 1b shows a simple chip multiprocessor, Fig. 1c shows a shared-cache chip multiprocessor, and Fig. 1d shows a multithreaded, shared-cache chip multiprocessor  ... 
doi:10.1109/tc.2011.199 fatcat:6cficu3jqnbr3eqxc6bgnis7ay

Parallel optical interconnects may reduce the communication bottleneck in symmetric multiprocessors

Jacques Henri Collet, Wissam Hlayhel, Daniel Litaize
2001 Applied Optics  
In this context, we suggest the introduction of simple point-to-point OI's for a SMP cache-coherent switch, i.e., for a VLSI switch that would emulate the shared-bus function.  ...  The interest for OI's comes from the potential increase of the transmission frequency and from the possible integration of such a high density of IO's on top of electronic chips to overcome packaging issues  ...  a shared bus to maintain the cache coherence with a snooping protocol.  ... 
doi:10.1364/ao.40.003371 pmid:18360362 fatcat:f53vxtdnybblxhpl3gulluizha

Proximity-aware directory-based coherence for multi-core processor architectures

Jeffery A. Brown, Rakesh Kumar, Dean Tullsen
2007 Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures - SPAA '07  
As the number of cores increases on chip multiprocessors, coherence is fast becoming a central issue for multi-core performance.  ...  This paper describes mechanisms to accelerate coherence for a multi-core architecture that has multiple private L2 caches and a scalable point-to-point interconnect between cores.  ...  Acknowledgments The authors would like to thank the anonymous reviewers for their helpful insights.  ... 
doi:10.1145/1248377.1248398 dblp:conf/spaa/BrownKT07 fatcat:y7c3zgv3dncirjggikdfmyfuwi

Design and Implementation of Inter-core Communication of Embedded Multiprocessor Based on Shared Memory

Yang Nie, Lili Jing, Pengyu Zhao
2016 International Journal of Security and Its Applications  
Two kinds of shared memory, on-chip local memory and on external memory, will be study.  ...  The whole system is connected AXI Interconnect, and the shared memory is used as a communication mechanism.  ...  Acknowledgments We would like to thank professor GE for stimulating discussions with respect to the topic of this paper and laboratory equipment.  ... 
doi:10.14257/ijsia.2016.10.12.03 fatcat:zaj3lpdz2rfqdbsj26u2ufnr2q

The Scalable Coherent Interface (SCI)

D.B. Gustavson, Qiang Li
1996 IEEE Communications Magazine  
There is rapidly increasing demand for very-high-performance networked communication for workstation clusters, distributed databases, multiprocessors, industrial data acquisition and control systems, shared  ...  access t o distributed data, and so on.  ...  and cache coherence protocols needed for multiprocessor applications.  ... 
doi:10.1109/35.533919 fatcat:icmnbvnsfffv7hzxejen5fd77m

An Efficient Cache Organization for On-Chip Multiprocessor Networks

Medhat Awadalla, Ahmed M. Sadek
2015 International Journal of Electrical and Computer Engineering (IJECE)  
It is based on the typical MESI cache coherence algorithm however it is tuned and tailored for the suggested architecture.  ...  This paper focuses on the interconnection design issues of area, power and performance of chip multi-processors with shared cache memory.  ...  CACHE COHERENCE WITH MESI WRITE BACK PROTOCOL In a shared memory multiprocessor system with a separate cache memory for each processor, it is possible to have many copies of any one instruction operand  ... 
doi:10.11591/ijece.v5i3.pp503-517 fatcat:nc4ftmxwivevpn5eaew3ypsmnm
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