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A self-test approach using accumulators as test pattern generators

A.P. Stroele
Proceedings of ISCAS'95 - International Symposium on Circuits and Systems  
Corizpared to file well-known selftest tnethods that insert test registers, the approach using accumulators saves the additional gates that are needed to iniplenient test registers, and it avoids pecfortnunce  ...  This paper unalyzes tlie patiern sequences produced by different types of accuriiulators and shows that they can achieve similar ,fault coverage as pseudo-random patterns.  ...  Since these accumulators can also be used as test response compactors, a complete self-test approach based on accumulators is feasible.  ... 
doi:10.1109/iscas.1995.523844 dblp:conf/iscas/Stroele95 fatcat:xnsokzrbd5hd5dowjt3e7emmve

Software-based self-testing methodology for processor cores

Li Chen, S. Dey
2001 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We then propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests.  ...  While memory BIST is commonly used for testing embedded memory cores, complex logic designs such as microprocessors are rarely tested with logic BIST.  ...  The self-testing step involves the application of the component tests using a software tester, which consists of an on-chip test pattern generation program, a test pattern application program, and a test  ... 
doi:10.1109/43.913755 fatcat:ors6roeymfgq5mmozi2mgg52te

Accumulator-based built-in self-test generator for robustly detectable sequential fault testing

I. Voyiatzis, N. Kranitis, D. Gizopoulos, A. Paschalis, C. Halatsis
2004 IEE Proceedings - Computers and digital Techniques  
In this paper an algorithm for the generation of single input change (SIC) pairs is presented, termed the accumulator-based SIC pair generation (ASG) algorithm; SIC pairs have been effectively utilised  ...  ASG is implemented in hardware utilising an accumulator whose inputs are driven by a barrel shifter.  ...  In [9, 10] two-pattern test generation using cellular automata was investigated.  ... 
doi:10.1049/ip-cdt:20040850 fatcat:257kgtuvbjckrjxj32uubibdzq

Design of accumulator Based 3-Weight Pattern Generation using LP-LSFR

G. Sindhu
2013 IOSR Journal of Electronics and Communication Engineering  
In this approach, the single input change patterns generated by a counter and a gray code generator are Exclusive-ORed with the seed generated by the low power linear feedback shift register [LP-LFSR].  ...  Since accumulators are commonly found in current VLSI chips, this scheme can be efficiently utilized to drive down the hardware of BIST pattern generation, as well.  ...  For pattern generators, we can use either a ROM with stored patterns, or a counter or a linear feedback shift register (LFSR).A response analyzer is a compactor with stored responses or an LFSR used as  ... 
doi:10.9790/2834-0738691 fatcat:so5ehu2bzvesbpgcljkxx6g2iq

Power-/energy-efficient BIST schemes for processor data paths

N. Kranitis, D. Gizopoulos, A. Paschalis, M. Psarakis, Y. Zorian
2000 IEEE Design & Test of Computers  
Wide use of portable battery-operated devices and the race toward low-power design and low-cost, low-weight packages, makes test power issues increasingly important. 1 When built-in self-test (BIST) is  ...  employed as a testing means for processing elements or other modules/cores, a relatively large number of uncorrelated pseudorandom test vectors are applied to the circuit, causing a significantly higher  ...  Another approach uses a new linear feedback shift register (LFSR)-based test pattern generator (TPG), which reduces power consumption by reducing the transition densities of test vectors generated by a  ... 
doi:10.1109/54.895003 fatcat:yjsjfrzdvjclvdggh47dwih43a

Embedded hardware and software self-testing methodologies for processor cores

Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng
2000 Proceedings of the 37th conference on Design automation - DAC '00  
We propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests.  ...  Currently, Built-In Self-Test (BIST) is the primary self-test methodology available and is widely used for testing embedded memory cores.  ...  The self-testing step involves the use of a software tester, which consists of an on-chip test pattern generation program, a test pattern application program, and a test response analysis program, as shown  ... 
doi:10.1145/337292.337599 dblp:conf/dac/ChenDSSC00 fatcat:m7k46u6t3ve37gn67e3bety56e

Self-Testing Analog Spiking Neuron Circuit

Sarah A. El-Sayed, Luis A. Camunas-Mesa, Bernabe Linares-Barranco, Haralampos-G. Stratigopoulos
2019 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)  
The self-test wrapper is a compact circuit composed of a low-precision ramp generator and a small digital block.  ...  In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. In particular, we propose a self-testable version of a spiking neuron circuit.  ...  Luis A. Camuñas-Mesa was funded by the VI PPIT through the Universidad de Sevilla.  ... 
doi:10.1109/smacd.2019.8795234 dblp:conf/smacd/El-SayedCLS19 fatcat:txg3ajwwqvevhiage74fpk67l4

Online self-repair of FIR filters

A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto
2003 IEEE Design & Test of Computers  
Acknowledgments This work is partially supported by Instituto Superiore per le ICT Mario Boella under contract Test D.O.C.: Quality and Reliability of Complex SoC.  ...  The system tests each module using an approach similar to (and reusing the same structures as) the POST mechanism just described.  ...  In test mode, a set of test patterns, called the mini bus test, feeds this bus.  ... 
doi:10.1109/mdt.2003.1198686 fatcat:tid6x7hcvbb6rc722b7e5d2ehu

Accumulator based BIST using Approximate Adders

KARUNAMURTHY Thilagavathi, DEY Satyapriya, POOJA Renuka, SATHASIVAM Sivanantham
2019 Journal of Electrical and Electronics Engineering  
In this paper, we present an accumulator based built-in self test (BIST) with approximate adders for single input change (SIC) test pattern generation.  ...  The experimental results show that proposed accumulator with approximate adder is a promising solution for test pattern generation in accumulator based BIST.  ...  The nbit SIC test pattern T {T 0 , T 1 … T n-1 } is generated using algorithm presented fig.1 .  ... 
doaj:885c02b62d7642dfbe655c8717383f8d fatcat:thv6b6a4dfadnpzgdrczlqfbjy

Implementation of Low Power TPG using LFSR and single input changing generator (SICG) for BIST Application: A Review

Namratha M R, Jyothi Pramal, Praveen J, Raghavendra A Rao
2015 IJIREEICE  
A novel test pattern generator which is more suitable for built in self test (BIST) structures used for testing of VLSI circuits.  ...  In this approach, the single input change patterns generated by a counter and a gray code generator are Exclusive-ORed with the seed generated by the low power linear feedback shift register [LP-LFSR].  ...  The linear feedback shift register (LFSR) is commonly used as a test pattern generator (TPG) in low overhead built-in self-test (BIST).  ... 
doi:10.17148/ijireeice.2015.3429 fatcat:36upg5ss4rfwvltaxo4cgvo2xa

A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores

M.H. Tehranipour, S.M. Fakhraie, Z. Navabi, M.R. Movahedin
2004 Journal of electronic testing  
In our proposed architecture, a self test program called BIST Program is stored in an embedded ROM as a vehicle for applying tests.  ...  In this paper, we have proposed a fuctional self-test methodology that is deterministic in nature.  ...  Acknowledgment The authors would like to thank Professor Krishnendu Chakrabarty of ECE Department of Duke University for his useful suggestions.  ... 
doi:10.1023/b:jett.0000023679.08518.bf fatcat:ps3ege2h65cojbbtfoux5opp7a

Optimal hardware pattern generation for functional BIST

Silvia Cataldo, Silvia Chiusano, Paolo Prinetto
2000 Proceedings of the conference on Design, automation and test in Europe - DATE '00  
The present paper addresses the computation of optimal seeds for an arbitrary sequential module to be used as hardware test pattern generator.  ...  Nevertheless the method is absolutely general, for sake of comparison with previous approaches, in this paper an accumulator based unit is assumed as pattern generator module.  ...  Acknowledgments The authors wish to thank A. Bergadano for implementig GASTBY, and A. Benso and R. Dorsch for the fruitfull discussions concerning the development of the tool.  ... 
doi:10.1145/343647.343784 fatcat:ftt5u5qtona7rlu5qoxhln2fy4

Design of Low Power TPG for BIST Using Reconfigurable Johnson Counter

M. Nandini Priya, R. Vivitadurga, U. Priya
2019 Zenodo  
Worked in Self-Test assumes an essential job in testing of VLSI circuits. Test designs created utilizing design generator is utilized to test the Circuit under Test.  ...  A Modern Low Power test design is created utilizing Reconfigurable Johnson Counter and Accumulator. A Low Power utilization gadget is basic for battery worked gadgets.  ...  Serial test pattern generator is used in test per scan and parallel test pattern generator is used in test per clock.  ... 
doi:10.5281/zenodo.2532996 fatcat:55whty7ejbherlrzugwbngdmve

BIST for systems-on-a-chip

Hans-Joachim Wunderlich
1998 Integration  
Core-providers offer RISC-kernels, embedded memories, DSPs, and many other functions, and built-in self-test is the appropriate method for testing complex systems composed of different cores.  ...  Special emphasis is put on deterministic BIST methods as they do not require any modifications of the core under test and help to protect intellectual property (IP).  ...  Figure 23 : 23 A typical accumulator structure used as test pattern generator. In each cycle the constant content of register c is added to register r.  ... 
doi:10.1016/s0167-9260(98)00021-2 fatcat:qenkm6odojampcjqguhbco6l6m

Design of BIST using Self-Checking Circuits for Multipliers

Nishant Govindrao Pandharpurkar, V. Ravi
2015 Indian Journal of Science and Technology  
This paper presents the novel design of Built-In-Self-Test (BIST) using self-checking circuits for bit array multipliers.  ...  Findings: Simulation results shows that implementation of this self-checking full adder into standard bit array multiplier minimizes the area overhead and power consumption by 25%-30% as compared to previous  ...  In this scheme, as name suggests, a sequence of two-pattern test vectors are generated.  ... 
doi:10.17485/ijst/2015/v8i19/77006 fatcat:nufjigrpnzb43bfkwxz5b76hom
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