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A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores

M.H. Tehranipour, S.M. Fakhraie, Z. Navabi, M.R. Movahedin
2004 Journal of electronic testing  
In our proposed architecture, a self test program called BIST Program is stored in an embedded ROM as a vehicle for applying tests.  ...  We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using  ...  Acknowledgment The authors would like to thank Professor Krishnendu Chakrabarty of ECE Department of Duke University for his useful suggestions.  ... 
doi:10.1023/b:jett.0000023679.08518.bf fatcat:ps3ege2h65cojbbtfoux5opp7a

Embedded software-based self-test for programmable core-based designs

A. Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, L. Chen, S. Dey
2002 IEEE Design & Test of Computers  
Because digital logic testers cannot do precise analog testing, externally testing mixed-Embedded Software-Based Self-Test for Programmable Core-Based Designs Embedded Systems 18 The programmable cores  ...  WITH THE GROWING popularity of system-ona-chip (SoC) architectures, demands for short time to market and rich functionality have driven design houses to adopt a new core-based SoC design flow.  ...  Figure 1 . 1 Embedded software-based self-testing concept. Figure 2 . 2 Embedded processor self-testing. Figure 3 . 3 Self-testing nonprogrammable cores in a SoC.  ... 
doi:10.1109/mdt.2002.1018130 fatcat:fyyiaiaoj5dvzf6otfkzjqx25m

Embedded software-based self-testing for SoC design

A. Krstic, W. C. Lai, K. T. Cheng, L. Chen, S. Dey
2002 Proceedings - Design Automation Conference  
After the programmable core on a System-on-Chip (SoC) has been self-tested, it can be reused for testing on-chip buses, interfaces and other non-programmable cores.  ...  In this paper, we give a survey and outline the roadmap and challenges of this emerging embedded software-based self-testing paradigm.  ...  CONCLUSIONS Embedded software-based self-testing has a potential to alleviate many of the current external tester-based and hardware BIST testing techniques for SoCs.  ... 
doi:10.1145/514009.514010 fatcat:2nluc3xsorg2zegsuuliffxv7i

Embedded software-based self-testing for SoC design

A. Krstic, W. C. Lai, K. T. Cheng, L. Chen, S. Dey
2002 Proceedings - Design Automation Conference  
After the programmable core on a System-on-Chip (SoC) has been self-tested, it can be reused for testing on-chip buses, interfaces and other non-programmable cores.  ...  In this paper, we give a survey and outline the roadmap and challenges of this emerging embedded software-based self-testing paradigm.  ...  CONCLUSIONS Embedded software-based self-testing has a potential to alleviate many of the current external tester-based and hardware BIST testing techniques for SoCs.  ... 
doi:10.1145/513918.514010 dblp:conf/dac/KrsticLCCD02 fatcat:wanljgmetzfb7pncwaxcsm3x5e

Code generation for core processors

Peter Marwedel
1997 Proceedings of the 34th annual conference on Design automation conference - DAC '97  
language programming for embedded software obsolete.  ...  Testing is simplified because test engineers know the components they have to test from previous designs.  ...  Generation of Self-Test Programs with Retargetable Compilers Testing of processor cores can be performed by running self-test programs on the processor to be tested.  ... 
doi:10.1145/266021.266073 dblp:conf/dac/Marwedel97 fatcat:t6nd6rrhxvd5rp26jliulgw7q4

HW-SW Framework for Multimedia Applications on MPSoC: Practice and Experience

Yan Liu, Renfa Li, Cheng Xu, Fei Yu
2009 Journal of Computers  
Constructing a intelligence surveillance system using embedded video server requires a sophisticated hardware/software framework for this system, and it should consider the performance, cost and energy  ...  This paper discusses the design and implementation of an intelligence surveillance system which uses embedded multimedia server as core computing platform.  ...  DSP/BIOS is a small core operating system running on the DSP core to provide basic operations.  ... 
doi:10.4304/jcp.4.3.238-244 fatcat:aqgi6l7wdzee3pjikw4b33mczi

Self-test methodology for at-speed test of crosstalk in chip interconnects

Xiaoliang Bai, Sujit Dey, Janusz Rajski
2000 Proceedings of the 37th conference on Design automation - DAC '00  
To enable self-testing of the interconnects, we have designed efficient on-chip test generators and error detectors to be embedded in necessary cores; while the test generators generate test vectors for  ...  Using a new highlevel crosstalk simulation technique, we have validated the selftest methodology, including the self-test structures inserted in the DSP chip. z z z z z z Figure 1 -(a) Glitch , (b) Delay  ...  Validation of the Self-Test Methodology To validate the self-test methodology, including the proper design and functioning of the test generators, error detectors and test controllers embedded in the DSP  ... 
doi:10.1145/337292.337597 dblp:conf/dac/BaiDR00 fatcat:ecan6yhlrbbg3bp4dldhijviai

Prototyping Embedded Dsp Systems - From Specification To Implementation

Zoran Salcic
2004 Zenodo  
purposes (e.g. generation of test inputs in real-time). • Self-tuning regulator (STR) for second order systems [3] using recursive least squares (RLS) algorithm for system parameter identification and  ...  Two soft core 32-bit processors (NIOS [ ]) are used in the system, one for frequency calculation and communication with the external environment via Internet, and the other one for testing and debugging  ... 
doi:10.5281/zenodo.38706 fatcat:navkxtet35ae7hpjep3xrbe6oi

Low-cost software-based self-testing of RISC processor cores

N. Kranitis, G. Xenoulis, D. Gizopoulos, A. Paschalis, Y. Zorian
2003 IEE Proceedings - Computers and digital Techniques  
a high fault coverage for the processor core.  ...  In this paper we present a low-cost software-based self-testing methodology for processor cores with the aim of producing compact test code sequences developed with a limited engineering effort and achieving  ...  Introduction The widely accepted System-on-Chip (SoC) design paradigm consists in most cases of one or more embedded processor cores surrounded by other cores for program and data storage, communication  ... 
doi:10.1049/ip-cdt:20030838 fatcat:gzhdjudm55ftxlcs5b45yf43fm

Soft Core Embedded Processor Based Built-In Self-Test of FPGAs

Bradley F. Dutton, Charles E. Stroud
2009 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems  
This paper presents the first implementation of Built-In Self-Test (BIST) of Field Programmable Gate Arrays (FPGAs) using a soft core embedded processor for reconfiguration of the FPGA resources under  ...  test, control of BIST execution, retrieval of BIST results, and fault diagnosis.  ...  There are a variety of designs which can be used for the embedded processor ranging from fast, full-custom register transfer level (RTL) designs, to highly configurable general purpose soft core microprocessors  ... 
doi:10.1109/dft.2009.51 dblp:conf/dft/DuttonS09 fatcat:r6tayxcdm5hf7j4wfwkz2cs5dm

Preesm: A dataflow-based rapid prototyping framework for simplifying multicore DSP programming

Maxime Pelcat, Karol Desnos, Julien Heulot, Clement Guy, Jean-Francois Nezan, Slaheddine Aridhi
2014 2014 6th European Embedded Design in Education and Research Conference (EDERC)  
Several tutorials are provided with the tool for fast initiation of C programmers to multicore DSP programming.  ...  This paper demonstrates PREESM capabilities by comparing simulation and execution performances on a stereo matching algorithm prototyped on the TMS320C6678 8-core DSP device.  ...  The code generation produces a self-timed code [13] , i.e. a static code for each core with automatic inter-core communication, cache management and synchronization.  ... 
doi:10.1109/ederc.2014.6924354 fatcat:6lyzuq4v25afti3prgdpfbldey

Implementing Multimodal Biometric Solutions in Embedded Systems [chapter]

Jingyan Wang, Yongping Li, Ying Zhang, Yuefeng Huang
2011 Biometrics - Unique and Diverse Applications in Nature, Science, and Technology  
In section 4, a new multi-biometrics system is designed for multi-core OMAP3 processor combing GPP and DSP cores, fusing iris and palmprint at sensor level (image level).  ...  Program optimization on DSP Because the TMS320C64x+ DSP core in OMAP3530 is a fixed-point processor and most of our algorithms are floating-point algorithms, we carry out fixed-point programming to the  ... 
doi:10.5772/15843 fatcat:kceebscyjjcfzj475i7ha56t4u

Embedded hardware and software self-testing methodologies for processor cores

Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng
2000 Proceedings of the 37th conference on Design automation - DAC '00  
Currently, Built-In Self-Test (BIST) is the primary self-test methodology available and is widely used for testing embedded memory cores.  ...  We propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests.  ...  Since the need for self-testing is most acute for highperformance processors, we propose a new software-based selftesting methodology for processors, which uses a software tester embedded in the processor  ... 
doi:10.1145/337292.337599 dblp:conf/dac/ChenDSSC00 fatcat:m7k46u6t3ve37gn67e3bety56e

DSP-Based Parallel Implementation of Speeded-Up Robust Features

Chao LIAO, Guijin WANG, Quan MIAO, Zhiguo WANG, Chenbo SHI, Xinggang LIN
2011 IEICE transactions on information and systems  
In this paper, we propose an efficient parallel computing framework for speeded-up robust features with an orientation towards multi-DSP based embedded system.  ...  We optimize modules in SURF to better utilize the capability of DSP chips. We also design a compact data layout to adapt to the limited memory resource and to increase data access bandwidth.  ...  Conclusion In this paper, we present a fast parallel implementation of SURF on DSP-based embedded systems.  ... 
doi:10.1587/transinf.e94.d.930 fatcat:bqxdevprtva77hsdyctqdi2mwq

Robust Automatic Speech recognition System Implemented in a Hybrid Design DSP-FPGA

Ali Aldahoud, Hamza Atoui, Mohamed Fezari
2013 International Journal of Signal Processing, Image Processing and Pattern Recognition  
Major contribution of this work are hybrid solution DSP and FPGA in real time speech recognition system design, the optimization of number of MAC-core within the FPGA this result is obtained by sharing  ...  The aim of this work is to reduce the burden task on the DSP processor by transferring a parallel computation part on a configurable circuits FPGA, in automatic speech recognition module design, signal  ...  Mokhtar Nibouche from Department of Electrical and Computer Engineering, University of the West of England Bristol UK for his support during training days on DSP boards.  ... 
doi:10.14257/ijsip.2013.6.5.29 fatcat:zus6xq32qvawjlz2n6yrppaez4
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