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Variation-aware thermal characterization and management of multi-core architectures
2008
2008 IEEE International Conference on Computer Design
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Experimental analysis based on live measurements on a special test-chip shows reduced on-chip heating with no performance loss, which improves the power/thermal efficiency of the chip at no cost. ...
We propose a technique that utilizes the existing on-chip sensor infrastructure to improve the inherent thermal imbalances among different cores in a multicore architecture. ...
We show that run-time assessment using on-chip sensor infrastructure can substitute for manufacturers' guidelines. ...
doi:10.1109/iccd.2008.4751874
dblp:conf/iccd/KursunC08
fatcat:biy2oyrykbdhzjpnmi2w5w6kju
On-chip delay measurement for silicon debug
2004
Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04
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In this paper we present an on-chip scheme for delay fault detection and performance characterization. ...
Performance characterization of such chips requires on-chip hardware and efficient debug schemes in order to reduce time to market and ensure shipping of chips with lower defect levels. ...
Townsend for helping us design the multiplier test circuits. ...
doi:10.1145/988952.988988
dblp:conf/glvlsi/DattaSRA04
fatcat:akyxsdekqfaippq5ke6e46l6by
Experimental estimation of chip shrinkage under cup-tip cutting with straight and radius cutters
2015
IOP Conference Series: Materials Science and Engineering
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In the given work we present the results of experimental estimation of chip shrinkage under turning with straight and radius cutters for two schemes of cutting: "direct" and "reverse". ...
The authors show the significant difference in the character and degree of chip shrinkage when working according to various schemes of cutting. 1 Corresponding author: A V Filippov -andrey.v.filippov@yandex.ru ...
First, it is conditioned by the thickness of the cut layer which is many times smaller for cup-tip tools than for the single-point ones. ...
doi:10.1088/1757-899x/91/1/012061
fatcat:ylkopd5hvrcw5jffsew2uyupfu
A 4ps amplitude reconfigurable impulse radiator with THz-TDS characterization method in 0.13µm SiGe BiCMOS
2016
2016 IEEE MTT-S International Microwave Symposium (IMS)
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In addition to performing frequency-domain measurements, for the first time, an ultrawideband THz Time-Domain Spectroscopy (THz-TDS) system is utilized to characterize the radiated signal in time-domain ...
The fully-integrated impulse radiator is implemented in a 0.13µm SiGe BiCMOS process. It has a die area of 1mm 2 and it consumes 170mW. ...
ACKNOWLEDGEMENT Authors acknowledge Mahdi Assefzadeh for designing the impulse receiving antenna, Eiji Kato for technical supports of the Advantest THz-TDS system, as well as RISC members for valuable ...
doi:10.1109/mwsym.2016.7540210
fatcat:sx6aniev3feejcvx2qgtdokl4y
Guest Editorial: Special Issue on Analog, Mixed-Signal, RF, and MEMS Testing
2012
Journal of electronic testing
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Test cost has gradually become a major portion of the overall product cost for System-on-Chips (SoCs). ...
In paper 8, Kulovic and Margala introduce a technique for on-chip voltage measurement. ...
Test cost has gradually become a major portion of the overall product cost for System-on-Chips (SoCs). ...
doi:10.1007/s10836-012-5330-3
fatcat:zolhbokpefbupc2maj22ebg3mi
Process and Reliability Sensors for Nanoscale CMOS
2012
IEEE Design & Test of Computers
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In this paper, we describe the use of sensing schemes that drive on-chip process and aging variation measurements in manufactured silicon. ...
The second and third case studies utilize a mix of presilicon process characterization data (as used in statistical timing/power analysis) and postsilicon measurements to predict the performance drift ...
A new class of on-chip reliability monitors has recently been demonstrated in silicon, targeted for a range of applications such as reliability characterization during process ramp up, chip lifetime projection ...
doi:10.1109/mdt.2012.2211561
fatcat:pobsapttyrbp3oqmjjhcl5mtrq
Power-Efficient Schemes via Workload Characterization on the Intel's Single-Chip Cloud Computer
2012
2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum
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The objective of this work is to evaluate the viability of implementing workload-aware dynamic power management schemes on a many-core platform, aiming at reducing power consumption for high performance ...
First approach is an off-line scheduling scheme where core voltage and frequency are set up beforehand based on the workload characterization of the application. ...
We would like to thank Intel Labs for providing us with SCC system in material transfer to conduct this research. ...
doi:10.1109/ipdpsw.2012.122
dblp:conf/ipps/Chaparro-BaqueroZLTL12
fatcat:otnf3zkpnjf67hyyu75fijasl4
On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS
2012
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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By virtue of the proposed scheme, the relationship between the rising and falling delay variations and the active area of the standard cells is experimentally shown for the first time. ...
The proposed measurement system are able to characterize rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling ...
Nakamura for the useful discussions. ...
doi:10.1109/tvlsi.2011.2162257
fatcat:dkuxonwu7nbrdcfb3warva5wdq
KLauS – A charge readout and fast discrimination chip for silicon photomultipliers
2012
Journal of Instrumentation
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For a duty cycle of 1 % a value of 25 µW per channel is achieved without affecting the readout capabilities of the chip. ...
In addition, a power gating scheme has been implemented to further decrease the average power consumption. ...
The low trigger jitter makes the chip a good candidate for experiments requiring precise timing information. ...
doi:10.1088/1748-0221/7/01/c01008
fatcat:srogx6fxuzhqtnx5fgwi64bpwy
Voltage binning under process variation
2009
Proceedings of the 2009 International Conference on Computer-Aided Design - ICCAD '09
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This paper proposes a statistical technique of yield computation for different voltage binning schemes using results of statistical timing and variational power analysis. ...
The paper formulates and solves the problem of computing optimal supply voltages for a given binning scheme. ...
Then a chip is good if it satisfies timing and power requirements at least at one supply voltage V i . ...
doi:10.1145/1687399.1687480
dblp:conf/iccad/ZolotovVX09
fatcat:pxyyzwqvebdy5irxj4rhzxx334
Exploring the effects of on-chip thermal variation on high-performance multicore architectures
2011
ACM Transactions on Architecture and Code Optimization (TACO)
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In this article, we propose a technique that leverages the on-chip sensor infrastructure as well as the capabilities of power/thermal management to effectively reduce the heating and minimize local hotspots ...
Hence, in the case of variation, the chip faces repetitive hotspots running on such cores. ...
(a) Generating a variation map for individual cores; (b) Using the variation map for accurate run-time thermal estimation.
Fig. 4. Experimental setup for real-time thermal imaging. ...
doi:10.1145/1952998.1953000
fatcat:qga2kma5i5hdffjggc3mongoam
Reference Power Supply Connection Scheme for Low-Power CMOS Image Sensors Based on Incremental Sigma-Delta Converters
2021
Electronics
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different connection scheme to supply and to drive the required reference signals across the image sensor on-chip column converters. ...
on-chip references generation and driving method. ...
Furthermore, the authors would like to express their gratitude to Guy Meynants and Adi Xhakoni, for their support. ...
doi:10.3390/electronics10030299
fatcat:gvzbfsmqabenflglvukgrhxml4
An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS
2011
16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)
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Thanks to the proposed system, a relationship between the rising and falling delay variations and the active area of the standard cells is experimentally shown for the first time. ...
The proposed characterizing system is able to measure rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling oscilloscope ...
The VLSI chips were fabricated through the chip fabrication program of VLSI Design and Education Center (VDEC), the University of Tokyo, with the collaboration by STARC. ...
doi:10.1109/aspdac.2011.5722162
dblp:conf/aspdac/ZhangITS11
fatcat:b74gij2hhjffxgo63sdgo76ebu
SPAD pixel with sub-ns dead-time for high-count rate applications
2021
IEEE Journal of Selected Topics in Quantum Electronics
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In this paper, we present the architecture and the experimental characterization of two chips including a novel SPAD sensing, and readout scheme designed to minimize deadtime (1.78 ns and 0.93 ns respectively ...
Thanks to its compact size, this novel pixel architecture can be easily integrated within high-resolution SPAD arrays for GHz applications. ...
The third one, hereafter named 6FF-chip, (Fig. 1 , right) features a 10 μm circular SPAD with a divide-by-6 readout scheme. ...
doi:10.1109/jstqe.2021.3124825
fatcat:yq2z2gkhvrfgbkdd5pa4fdklde
On-Chip Testing Schemes of Through-Silicon-Vias (TSVs) in 3D Stacked ICs
2017
Advances in Science, Technology and Engineering Systems
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This paper presents on-chip testing structures to characterize and detect faulty Through Silicon Vias (TSVs) in 3D ICs technology. 3D Gunning Transceiver Logic (GTL) I/O testing is proposed to characterize ...
GSG) and ground-signal-signal-ground (GSSG) 3D vias configurations are used as a test vehicle for 3D interconnect characterization and test. ...
This will imply that each one will have a different oscillating frequency and thus a different counting value, which can be scanned out for off-chip testing. ...
doi:10.25046/aj0203159
fatcat:oz57blbpqbf7bi2mqc5xmpgady
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