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A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS

Ganesh Balamurugan, Joseph Kennedy, Gaurab Banerjee, James E. Jaussi, Mozhgan Mansuri, Frank O'Mahony, Bryan Casper, Randy Mooney
2008 IEEE Journal of Solid-State Circuits  
We present a scalable low-power I/O transceiver in 65 nm CMOS, capable of 5-15 Gbps operation over single-board and backplane FR4 channels with power efficiencies between 2.8-6.5 mW/Gbps.  ...  Index Terms-Electrical signaling, high-speed I/O, I/O power optimization, inductive termination, low-power equalization, lowpower I/O, passive clock distribution, power-efficient links, scalable circuits  ...  CONCLUSION A 5-15 Gbps scalable low-power I/O transceiver suitable for parallel links has been implemented in 65 nm CMOS.  ... 
doi:10.1109/jssc.2008.917522 fatcat:4as73walofh4nkiz2cr2aiy2ja

The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

Amlan Ganguly, M. Ahmed, Rounak Singh Narde, Abhishek Vashist, Md Shamim, Naseef Mansoor, Tanmay Shinde, Suryanarayanan Subramaniam, Sagar Saxena, Jayanti Venkataraman, Mark Indovina
2018 Journal of Low Power Electronics and Applications  
State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates.  ...  This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit.  ...  The high speed serial I/O channels are adopted from 65 nm designs and are shown to have a bandwidth of 15 Gbps with an energy consumption of 5 pJ/bit [108] .  ... 
doi:10.3390/jlpea8010005 fatcat:mtmupptnb5atzjlyoamee47k2a

RFIC 2020 Program

2020 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)  
beams in a 65-nm CMOS technology.  ...  A prototype of the SATCOM transceiver is fabricated in a standard 65-nm CMOS process.  ...  A modulator that provides outphasing signals to synthesize RF-PWM without a narrow pulse-width limitation is proposed. The Cartesian transmitter is implemented in a 65-nm CMOS process.  ... 
doi:10.1109/rfic49505.2020.9218389 fatcat:fqkpw3oau5gzpoi3gscgb7kwhi

An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links

Md Shahriar Shamim, Jagan Muralidharan, Amlan Ganguly
2015 Proceedings of the 9th International Symposium on Networks-on-Chip - NOCS '15  
finally getting routed from the I/O to the internal cores there.  ...  However, in a larger system consisting of several multicore chips across a board or in a System-in-Package (SiP), the performance is limited by the communication among and within these chips.  ...  The bandwidth of this I/O is 15 Gbps and its energy consumption is 5 pJ/bit, i.e. a power dissipation of 75 mW at 15Gbps [23] .  ... 
doi:10.1145/2786572.2786581 dblp:conf/nocs/ShamimMG15 fatcat:vmf5r324ejamvc5yopfobcfquq

Optical Interconnects Finally Seeing the Light in Silicon Photonics: Past the Hype

Hosam Mekawey, Mohamed Elsayed, Yehea Ismail, Mohamed A. Swillam
2022 Nanomaterials  
size lower than 5 nm.  ...  The potential of a slot waveguide is investigated as a new foundation since it allows for guiding and confining light into low index regions of a few tens of nanometers in cross-section.  ...  This approach resulted in an optical link of 5 Gbps speed with a 15 pJ/bit efficiency [49] .  ... 
doi:10.3390/nano12030485 pmid:35159830 pmcid:PMC8840221 fatcat:dxze3ntk6fapvb7bc63yhtniaq

A Review of 5G Front-End Systems Package Integration [article]

Atom O. Watanabe, Muhammad Ali, Sk Yeahia Been Sayeed, Rao R. Tummala, P. Markondeya Raj
2020 arXiv   pre-print
Major challenges arise in the packaging of radio-frequency front-end modules because of the stringent low signal-loss requirements in the millimeter-wave frequency bands, and precision-impedance designs  ...  In order to meet the data rate and efficiency metrics, 5G networks have emerged as a follow-on to 4G, and projected to have 100X higher wireless date rates and 100X lower latency than those with current  ...  (Qualcomm, QTM052) Antennas 64 -256 16 -32 4 -8 PA power 33 dBm 19 dBm 10-15 dBm (6-8 dBm usually) 28 nm CMOS DC power for four elements: 360 -380 mW Power consumption per channel < 100  ... 
arXiv:2009.07208v1 fatcat:7darv6meofb6znezmmurla24am

An 80 mW 40 Gb/s 7-Tap T/2-Spaced Feed-Forward Equalizer in 65 nm CMOS

Afshin Momtaz, Michael M. Green
2010 IEEE Journal of Solid-State Circuits  
A 7-tap 40 Gb/s FFE using a 65 nm standard CMOS process is described.  ...  A number of broadbanding and calibration techniques are used, which allow high-speed operation while consuming 80 mW from a 1 V supply.  ...  The FFE core occupies 0.75 mm in a 65 nm CMOS process and consumes 65 mW from a 1 V supply, making it the lowest power consuming FFE published so far (Table I) .  ... 
doi:10.1109/jssc.2009.2039268 fatcat:vrg3nilkbfes3eyqyljohhr5tu

An Energy-Efficient and Bandwidth-Scalable DWDM Heterogeneous Silicon Photonics Integration Platform

Di Liang, Sudharsanan Srinivasan, Geza Kurczveil, Bassem Tossoun, Stanley Cheung, Yuan Yuan, Antoine Descos, Yingtao Hu, Zhihong Huang, Peng Sun, Thomas Van Vaerenbergh, Chong Zhang (+5 others)
2022 IEEE Journal of Selected Topics in Quantum Electronics  
Here we review our innovations on a special heterogeneous III-V-on-silicon platform, and the development of a dense wavelength division multiplexed (DWDM) transceiver.  ...  A metal-oxide-semiconductor capacitor phase shifter is a mission critical structure to provide athermal and efficient tuning for deinterleavers and microring resonators, and high-speed modulation.  ...  A 5 μm in radius MOSCAP microring modulator with 15 nm-thick Al 2 O 3 gate oxide only needs aV pp of 2 V for 25 Gb/s operation, and consumes 2 mW modulator power (i.e., 80 fJ/bit) based on the calculation  ... 
doi:10.1109/jstqe.2022.3181939 fatcat:p3hf2g4ztjbrlme4ssz5zy6vn4

Integration of III-V lasers on Si for Si photonics

Mingchu Tang, Jae-Seong Park, Zhechao Wang, Siming Chen, Pamela Jurczak, Alwyn Seeds, Huiyun Liu
2019 Progress in Quantum Electronics  
This paper reviews the latest developments on telecommunication wavelength III-V lasers integrated on Si substrates, in terms of integration methods and laser performance.  ...  few dollars per gigabit per second (Gb/s) of input/output (I/O) bandwidth to less than a few cents per Gb/s [13] [14] [15] .  ...  A telecommunication wavelength (1578 nm) lasing peak appeared under CW optical pump at temperature 4.5 K with an effective threshold power of 1.6 mW, as shown in Fig. 15(c ).  ... 
doi:10.1016/j.pquantelec.2019.05.002 fatcat:nqs4e5p4y5ht7fvwyfocvsvckq

Roadmap of optical communications

Erik Agrell, Magnus Karlsson, A R Chraplyvy, David J Richardson, Peter M Krummrich, Peter Winzer, Kim Roberts, Johannes Karl Fischer, Seb J Savory, Benjamin J Eggleton, Marco Secondini, Frank R Kschischang (+7 others)
2016 Journal of Optics  
Quantum Communication is the art of transferring an unknown quantum state from one location, Alice, to a distant one, Bob.  ...  This is a non-trivial task because of the quantum no-cloning theorem which prevents one from merely using only classical means.  ...  MB-P was supported in part by the US National Science Foundation.  ... 
doi:10.1088/2040-8978/18/6/063002 fatcat:vo3kd4v66vbwtjojvr4mmasn6u

State of the Art and Perspectives on Silicon Photonic Switches

Xin Tu, Chaolong Song, Tianye Huang, Zhenmin Chen, Hongyan Fu
2019 Micromachines  
high-throughput computing, due to their low power consumption (Picojoules per bit), large bandwidth (Terabits per second) and high-level integration (Square millimeters per port).  ...  It starts with a review of three types of fundamental switch engines, i.e., Mach-Zehnder interferometer, micro-ring resonator and micro-electro-mechanical-system actuated waveguide coupler.  ...  0.165 [73] E-O MZI 8 × 8 Double Layer - - - - 0.675 [41] SJTU 16 × 16 Benes 14 5 −10 3.2 ns 1.2 10.7 × 4.4 [74] CAS T-O MZI 32 × 32 18.5 515 1.2 ns 0.54 12.1 × 5.2 [75] E-O MZI 64 × 64 Benes 12 −30  ... 
doi:10.3390/mi10010051 pmid:30642100 pmcid:PMC6356747 fatcat:hus2b3gfuzdq3ee6qmefqr6vzm

Trends in Emerging On-Chip Interconnect Technologies

Sudeep Pasricha, Nikil Dutt
2008 IPSJ Transactions on System LSI Design Methodology  
In deep submicron (DSM) VLSI technologies, it is becoming increasingly harder for a copper based electrical interconnect fabric to satisfy the multiple design requirements of delay, power, bandwidth, and  ...  interconnects are becoming increasingly susceptible to parasitic resistance and capacitance with shrinking process technology and rising clock frequencies, which poses serious challenges for interconnect delay, power  ...  In an FDMA interconnect, frequency bands of I/O channels can be allocated between 5-105 GHz with a bandwidth of approximately 5-20 GHz in each channel and sustaining a minimum data rate of 5-40 Gb/s depending  ... 
doi:10.2197/ipsjtsldm.1.2 fatcat:sscok66cfjfhrjw3zpri4zr75e

High speed test interface module using MEMS technology

Nabeeh Kandalaft, Ali Attaran, Rashid Rashizadeh
2015 Microelectronics and reliability  
Fig. 5 . 5 14: Contact spring's top view. 69 Fig. 5 . 695 15 : Cross section of the through holes.  ...  This can work for low count I/O pins where the traces are in the range of 4 cm long. However, for current ATE solutions with high I/O pin count devices require large size test fixtures.  ...  It is adaptable to variable die sized, and has the capability to be scalable to fit many types of I/O pins. It can support small pitch requirement for the next generation ICs.  ... 
doi:10.1016/j.microrel.2014.11.010 fatcat:hela63ims5fxjeu4df3ylumex4

The Phase-I Trigger Readout Electronics Upgrade of the ATLAS Liquid Argon Calorimeters [article]

G. Aad, A. V. Akimov, K. Al Khoury, M. Aleksa, T. Andeen, C. Anelli, N. Aranzabal, C. Armijo, A. Bagulia, J. Ban, T. Barillari, F. Bellachia (+186 others)
2022 arXiv   pre-print
The new system, installed during the second Large Hadron Collider Long Shutdown, increases the trigger readout granularity by up to a factor of ten as well as its precision and range.  ...  Major contributors of computing resources are listed in Ref. [44] .  ...  The crucial computing support from all WLCG partners is acknowledged gratefully, in particular from CERN, the ATLAS Tier-1 facilities at TRIUMF (Canada), NDGF (Denmark, Norway, Sweden), CC-IN2P3 (France  ... 
arXiv:2202.07384v1 fatcat:msce2cxcobgvflnwrxtwwnuyyi

Memory leads the way to better computing

H.-S. Philip Wong, Sayeef Salahuddin
2015 Nature Nanotechnology  
in advancing computing by a thousandfold by 2015.  ...  The report itself was drawn from the results of a series of meetings over the second half of 2007, and as such reflects a snapshot in time.  ...  Combined with voltage mode circuits and careful management of overhead, a power level as low as 14 mW at 6 Gbps can be demonstrated, or 2 pJ per bit [117] .  ... 
doi:10.1038/nnano.2015.29 pmid:25740127 fatcat:d6iiuuwcozbxlgn4kxxzdzwd4m
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