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A high-swing CMOS telescopic operational amplifier

K. Gulati, Hae-Seung Lee
1998 IEEE Journal of Solid-State Circuits  
Index Terms-CMOS analog integrated circuits, feedback, gain enhancement, op-amp, operational amplifier, replica tail, telescopic. worked on circuit techniques for minimizing susceptibility of DRAM's to  ...  A high-swing, high-performance CMOS telescopic operational amplifier is described.  ...  Varghese, A. Shabra, P. M. Naik, and D. A. Martin for their help. The fabrication was provided by MOSIS.  ... 
doi:10.1109/4.735542 fatcat:do4yorvv3bg4xbrecuwt4muvfy

A high-swing 2-V CMOS operational amplifier with replica-amp gain enhancement

P.C. Yu, Hae-Seung Lee
1993 IEEE Journal of Solid-State Circuits  
Abstrtict-A general gain-enhancement technique for operational amplifiers using a replica amplifier is described.  ...  Among the advantages of the replica-amp technique are low supply, high swing, and effectiveness with resistive loads. This technique has been demonstrated in a 1.2-pm CMOS two-stage op amp.  ...  The key bottleneck is the operational amplifier, which typically requires high openloop gain and high-frequency response to minimize errors in the output voltage, and high output swing to maximize the  ... 
doi:10.1109/4.261993 fatcat:caxzkfhh3faxvhhfnzedoahbma

High Performance CMOS Charge Pumps for Phase-locked Loop

Labonnah Farzana Rahman, NurHazliza Bt Ariffin, Mamun Bin Ibne Reaz, Mohammad Marufuzzaman
2015 Transactions on Electrical and Electronic Materials  
This paper presents a review of various CMOS CP schemes that have been implemented for PLLs and the relationship between the CP parameters with PLL performance.  ...  The majority of the researchers use a charge pump (CP) to obtain high performance from PLLs.  ...  A dual error amplifier CP with two replica-feedback amplifiers, also known as unity gain op-amp.  ... 
doi:10.4313/teem.2015.16.5.241 fatcat:swwbn6ac7ng6hov2cwxwd6nvy4

Low-Voltage Wireless Analog CMOS Circuits toward 0.5V Operation

Toshimasa MATSUOKA, Jun WANG, Takao KIHARA, Hyunju HAM, Kenji TANIGUCHI
2010 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
This paper introduces several techniques for achieving RF and analog CMOS circuits for wireless communication systems under ultra-low-voltage supply, such as 0.5 V.  ...  Forward body biasing and inverterbased circuit techniques were applied in the design of a feedforward Δ-Σ A/D modulator operating with a 0.5 V supply.  ...  Chip fabrication in this study was also supported by the University of Tokyo in collaboration with Synopsys, Inc. and Cadence Design Systems, Inc.  ... 
doi:10.1587/transfun.e93.a.356 fatcat:ogoh7pdfejeftmrpfzi5mukjna

Current Conveyor: Novel Universal Active Block

Indu Prabha Singh, Kalayan Singh, S. N. Shukla
2015 SAMRIDDHI A Journal of Physical Sciences Engineering and Technology  
A detailed study is presented here for its applications.  ...  Today these systems are replacing the conventional Op-amp in so many applications such as active filters, analog signal processing, and converters.  ...  (a) A composite CCII+ with enhanced Zx resembling an operational floating conveyor. (b) A composite CCII-with a different technique to lower Zx. (c) A composite CCII+ with enhanced Yx.  ... 
doi:10.18090/samriddhi.v1i1.1577 fatcat:dfwvw3ko4bethc6ec5nhawp2om

A 107.4 dB SNR Multi-Bit Sigma Delta ADC With 1-PPM THD at $-$0.12 dB From Full Scale Input

Jian-Yi Wu, Zhenyong Zhang, Rajaram Subramoniam, Franco Maloberti
2009 IEEE Journal of Solid-State Circuits  
A second order sigma delta modulator (SDM) with a 5-bit quantizer has been presented using several novel techniques: simplified DAC arrays for easy implementation, high-order truncation noise shaping for  ...  increased tolerance to analog imperfections, and an extended dynamic range for a maximum input signal swing of up to 0 12 dB FS (Full Scale).  ...  ACKNOWLEDGMENT The authors gratefully appreciate the project and support from the Data Conversion Division of National Semiconductor.  ... 
doi:10.1109/jssc.2009.2032753 fatcat:u4mkukzmzbgq7htn5irixnjluu

A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique

Rui Wang, U-Fat Chio, Sai-Weng Sin, U. Seng-Pan, Zhihua Wang, Rui Paulo Martins
2012 2012 Proceedings of the ESSCIRC (ESSCIRC)  
This paper presents a 12-bit 110MS/s 4-stage pipelined SAR ADC integrated through a single low-gain op-amp.  ...  A ratiobased GEC (Gain Error Calibration) technique based on op-amp sharing is proposed to reduce the complexity of digital calibration circuit.  ...  High Speed Current-mirror Low-Gain Op-Amp As described in the previous section, the open-loop gain of the op-amp should be at least 30dB, and thus a 33dB open-loop gain op-amp is designed here for the  ... 
doi:10.1109/esscirc.2012.6341336 dblp:conf/esscirc/WangCSUWM12 fatcat:riftycib3jewrmhg46dcm45qqe

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

C.C. Enz, G.C. Temes
1996 Proceedings of the IEEE  
In this paper, some old and some new circuit techniques will be described for the compensation of the amplifier most important nonideal effects including the noise (mainly thermal and llf noise), the input-referred  ...  Also, the achievable aniplijier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing.  ...  Both improvements are especially significant for low-supply voltage circuits, which have limited signal swings and where the op-amp gain may be low since headroom for cascoding may not be available.  ... 
doi:10.1109/5.542410 fatcat:fempn6qbafawzer4oyncfcp52i

A 2-GHz Highly Linear Efficient Dual-Mode BiCMOS Power Amplifier Using a Reconfigurable Matching Network

Hajir Hedayati, Mohamed Mobarak, Guillaume Varin, Philippe Meunier, Patrice Gamand, Edgar Sanchez-Sinencio, Kamran Entesari
2012 IEEE Journal of Solid-State Circuits  
A highly linear, efficient, two-stage power amplifier for high-data-rate wireless applications is presented.  ...  The experimental results show a gain of 13 dB and a maximum output power of 23 dBm with a PAE of 38%. The 1-dB output power compression point is 21 dBm with a 32% PAE.  ...  Dulger and K. Nam for their help on EVM and ACLR measurements.  ... 
doi:10.1109/jssc.2012.2203460 fatcat:bhspjg3jezfr5e6wfpumfmnebm

Comparative Analysis of CMOS Operational Amplifiers with Dynamic Offset Cancellation

Ara Abdulsatar Assim Assim, Evgenii Balashov
2021 Zenodo  
In this thesis, by using two different techniques for removing offset voltage (chopping and auto-zeroing), five low offset operational amplifiers were designed.  ...  The given work is devoted to designing and implementing different dynamic offset cancellation techniques for 50 nm technology CMOS operational amplifiers.  ...  Gain Gain is among the most crucial parameters of an amplifier, op-amps have very high gains especially at low frequency operations [15] .  ... 
doi:10.5281/zenodo.5517262 fatcat:4pnxu4iwofg63lmyjt5txvf2me

A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS

Ganesh Balamurugan, Joseph Kennedy, Gaurab Banerjee, James E. Jaussi, Mozhgan Mansuri, Frank O'Mahony, Bryan Casper, Randy Mooney
2008 IEEE Journal of Solid-State Circuits  
We present a scalable low-power I/O transceiver in 65 nm CMOS, capable of 5-15 Gbps operation over single-board and backplane FR4 channels with power efficiencies between 2.8-6.5 mW/Gbps.  ...  Low-power operation is enabled by passive equalization through inductive link termination, active continuous-time RX equalization, global TX/RX clock distribution with on-die transmission lines, and low-noise  ...  For such an amplifier, while its bandwidth varies approximately linearly with bias current, the gain remains fairly constant.  ... 
doi:10.1109/jssc.2008.917522 fatcat:4as73walofh4nkiz2cr2aiy2ja

An Optical Interconnect Transceiver at 1550 nm Using Low-Voltage Electroabsorption Modulators Directly Integrated to CMOS

Jonathan E. Roth, Samuel Palermo, Noah C. Helman, David P. Bour, David A. B. Miller, Mark Horowitz
2007 Journal of Lightwave Technology  
A low-voltage, 90-nm CMOS optical interconnect transceiver operating at 1550-nm optical wavelength is presented.  ...  At the receiver side, a sensitivity of −15.2 dBm is obtained with an integrating/double-sampling front end.  ...  Fig. 4 shows the pulsed-cascode output stage which accepts both a "low" input IN low that swings between the Gnd and the nominal chip Vdd and a "high" input IN high with the same data value that has been  ... 
doi:10.1109/jlt.2007.909334 fatcat:pssegkj4wvdofaqcxen2mktbzu

A Supply Pushing Reduction Technique for LC Oscillators Based on Ripple Replication and Cancellation

Yue Chen, Yao-Hong Liu, Zhirui Zong, Johan Dijkhuis, Guido Dolmans, Robert Bogdan Staszewski, Masoud Babaie
2019 IEEE Journal of Solid-State Circuits  
A ripple replication block (RRB) generates an amplified ripple replica at the gate terminal of the tail current source to stabilize the oscillator's tail current and thus its oscillating amplitude.  ...  In this paper, we propose a method to suppress supply pushing of an LC oscillator such that it may directly operate from a switched-mode dc-dc converter generating fairly large ripples.  ...  Mehrpoo, A. Akhnoukh, J. Gong, and B. Patra, all from the Delft University of Technology, for technical discussions and assistance.  ... 
doi:10.1109/jssc.2018.2871195 fatcat:52y5whgonfcghmbugqogojucom

Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS

Prakash Harikumar, J Jacob Wikner
2015 2015 IEEE International Symposium on Circuits and Systems (ISCAS)  
The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages.  ...  Utilizing metrics such as phase margin, unity-gain frequency and total compensation capacitance, the advantages of the reversed nested indirect compensation technique are illustrated for high-speed multi-stage  ...  Acknowledgments It has been an arduous, oft-enervating trek. I am beholden to those who helped me prevail.  ... 
doi:10.1109/iscas.2015.7168617 dblp:conf/iscas/HarikumarW15 fatcat:vedlais3pfdh3j3liiohu73lxy

A Power Scalable and Low Power Pipelined ADC [chapter]

Imran Ahmed
2010 Pipelined ADC Design and Enhancement Techniques  
A current modulation technique is used to avoid weakly inverted transistors for low bias currents, thus avoiding less accurate simulation, poorer matching, and increased bias sensitivity.  ...  There are of course others who shall remain nameless, whose support and encouragement during the lows of lows and highs of highs was both welcome and much needed.  ...  .): 23: PMOS gain boosting opamp 24: high gain replica biased based switched opamp (note replica bias amps are switched) TransistorsFig. 5 - 5 MS3 and MS4 are used in parallel with the replica bias opamp  ... 
doi:10.1007/978-90-481-8652-5_7 fatcat:2s7yeyvqonhrpdvhxqseowxwl4
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