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Survey on Coarse Grained Reconfigurable Architectures

Vaishali Tehre, Ravindra Kshirsagar
2012 International Journal of Computer Applications  
Recent advancement in the semiconductor technology allow the hardware engineers to integrate complex modules like processors, peripheral devices, and memory in a single System-on-a-Chip (SoC); where testability  ...  Hence a lot of research is going on to implement CGRA in SOC because Coarse-grained reconfigurable architecture can provide both performance and flexibility.  ...  The fundamental computation component in this architecture is a 4-bit Arithmetic array (ALU) with 16 instructions. Each ALU has adjacent switchbox which serves as a cross point with 64 connections.  ... 
doi:10.5120/7429-0104 fatcat:nb5kpk3ja5g2dlilbeudebl77a

Coarse-Grained Reconfigurable Array: Architecture and Application Mapping

Kiyoung Choi
2011 IPSJ Transactions on System LSI Design Methodology  
RC array is an 8 × 8 array of ALUs that performs 16-bit operations based on SIMD programming model.  ...  On the other hand, a CGRA typically consists of an array of ALUs and registers, and the reconfiguration is performed at the word-level.  ...  He is also interested in computer architecture and especially in configurable and reconfigurable computer architecture design.  ... 
doi:10.2197/ipsjtsldm.4.31 fatcat:46ph7de3wreexmn6wl3ealzzhy

Area-Efficient Reconfigurable Architecture for Media Processing

2008 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
fine-grained operations are executed with the cooperation of a host processor.  ...  Implementation results show that a multi-standard video decoding can be achieved by the proposed reconfigurable architecture with 1.1 × 1.4 mm 2 in a 90 nm CMOS technology.  ...  Acknowledgements The authors are grateful to the members of the system architecture group, platform development center, Matsushita Electric Industrial Co., Ltd, for their helpful comments.  ... 
doi:10.1093/ietfec/e91-a.12.3651 fatcat:wfypwsc3mnce3mnixt5kcylbxq

A Survey on Dynamically Reconfigurable Processors

2006 IEICE transactions on communications  
Hideharu AMANO †a) , Member SUMMARY Dynamically reconfigurable processors are consisting of an array of processing elements whose functions and interconnections can be dynamically changed. 9 commercial  ...  systems are picked up, and their array structures, processing elements and interconnection architectures are classified.  ...  Unlike FPGAs based on the fine-grain LUTs, a dynamically reconfigurable processor is a coarse grain programmable device.  ... 
doi:10.1093/ietcom/e89-b.12.3179 fatcat:z7uep5s5jfehtkgepanutfwgye

A 90k gate "CLB" for Parallel Distributed Computing [chapter]

Bruce Schulman, Gerald Pechanek
2000 Lecture Notes in Computer Science  
A reconfigurable architecture using distributed logic block processing elements (PEs) is presented.  ...  This distributed processor uses a lowcost interconnection network and local indirect VLIW memories to provide efficient algorithm implementations for portable battery operated products.  ...  Based upon present application evaluations, two banks of 512x32-bits are typically proposed, although there is no architecture limit.  ... 
doi:10.1007/3-540-45591-4_114 fatcat:hku55mtay5dxbieqqe6z2upd34

The Reconfigurable Instruction Cell Array

Sami Khawam, Ioannis Nousias, Mark Milward, Ying Yi, Mark Muir, Tughrul Arslan
2008 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
This paper presents a novel instruction cell-based reconfigurable computing architecture for low-power applications, thereafter referred to as the reconfigurable instruction cell array (RICA).  ...  For the development of the RICA, a top-down software driven approach was taken and revealed as one of the key design decisions for a flexible, easy to program, low-power architecture.  ...  The reconfigurable array is based on the D-fabrix consisting of a homogeneous grid of 4-bit ALU units.  ... 
doi:10.1109/tvlsi.2007.912133 fatcat:zibqfwr7obehbd7pcgtox7ponq

Survey of reconfigurable architectures for multimedia applications

T. Cervero, S. López, G. M. Callicó, F. Tobajas, V. de Armas, J. López, R. Sarmiento, Teresa Riesgo, Eduardo de la Torre, Leandro Soares Indrusiak
2009 VLSI Circuits and Systems IV  
As a result, this paper establishes the benefits and drawbacks of the different dynamically reconfigurable architectures for multimedia applications according to their system-level design.  ...  In order to sort all the information generated about this issue, this paper reviews the most recent reconfigurable architectures for multimedia applications.  ...  On the next level of connectivity is a switch block array communicating all quadrants. Finally the Indium bump interconnection array communicates the processor with the CAP.  ... 
doi:10.1117/12.821713 fatcat:kpgwm6tdkfan7hpn7fojpgwlq4

Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing

Zain-ul-Abdin, Bertil Svensson
2009 Microprocessors and microsystems  
systems, the architectures of reconfigurable devices have evolved to coarse-grained compositions of functional units or program controlled processors, which are operated in a coordinated manner to improve  ...  In this survey we explore the field of coarse-grained reconfigurable computing on the basis of the hardware aspects of granularity, reconfigurability, and interconnection networks, and discuss the effects  ...  Dan Hammerstrom) for their valuable feedback during the internal review of the paper.  ... 
doi:10.1016/j.micpro.2008.10.003 fatcat:k4c63f4k2zbc5a4mfr3vfwqkfe

A reconfigurable arithmetic array for multimedia applications

Alan Marshall, Tony Stansfield, Igor Kostarnov, Jean Vuillemin, Brad Hutchings
1999 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays - FPGA '99  
In this paper we describe a reconfigurable architecture optimised for media processing, and based on 4-bit ALUs and interconnect. Keywords Reconfigurable computing, multimedia, 4-bit ALU, FPGA.  ...  Long reconfiguration times, measured in tens of ms, also limit the value of reconfigurability in situations such as video processing.  ...  We would also like to thank John Lumley and Nick Wainwright of HP Laboratories, Bristol for their extensive support throughout the project.  ... 
doi:10.1145/296399.296444 dblp:conf/fpga/MarshallSKVH99 fatcat:5yui35hmsracdnhtny6yimfqvi

TeraOPS hardware: A new massively-parallel MIMD computing fabric IC

Anthony Mark Jones, Mike Butts
2006 2006 IEEE Hot Chips 18 Symposium (HCS)  
2 Traditional architectures are reaching limits in performance, scalability and ease of development Single CPUs and DSPs are reaching limits of extending performance Ordinary multi-core processors won't  ...  Ambric architecture is a member of an emerging class: Reconfigurable Processing Array (RPA) -Hundreds of processing elements such as CPUs, ALUs, memories… -Rich, word-wide, reconfigurable interconnect  ...  Ambric's architecture economically scales with Moore's Law The bric is the physical building-block -Two CU-RU pairs -8 CPUs -13KB RAM Brics connect by abutment to form a core array -CU quads  ... 
doi:10.1109/hotchips.2006.7477853 fatcat:gmlq7ucibjfsdpgeevacv55hbq

Review of recent trends in Coarse Grain Reconfigurable Architectures for signal processing applications

Sridharan M.., R. Ramya
2018 Advances in Systems Science and Applications  
Also, the constraints on memory bandwidth in the traditional von Neumann architectures along with the slow growth in the battery capacity demands a paradigm shift in computer architecture design.  ...  The research shows that the coarse grain reconfigurable architectures with heterogeneous processing elements are a better option for system design in DSP applications which exploit granularity matching  ...  COARSE GRAIN RECONFIGURABLE ARCHITECTURES The coarse grain reconfigurable architectures compromise on the flexibility of FPGA to match with the performance of ASIC by limiting themselves to a particular  ... 
doi:10.25728/assa.2018.18.1.508 fatcat:eihxjjbe5fbtfidecoa4j7sv6y

Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays

Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
2008 2008 Symposium on Application Specific Processors  
of a cluster of ALUs with flexible interconnect.  ...  While most CGRA designs feature an array cell of the order of an ALU, this paper proposes a new kind of coarse grained array, called EGRA (Expression-Grained Reconfigurable Array), featuring a cell composed  ...  Instead, the architecture we propose in this paper (Figure 1d ) employs an array cell consisting of a group of ALUs with customizable capabilities.  ... 
doi:10.1109/sasp.2008.4570782 dblp:conf/sasp/AnsaloniBP08 fatcat:y72l6rz5eng25kmmdf4qu7dcly

FPGA Implementation of On-Chip Network

N Murali Krishna
2018 DJ Journal of Advances in Electronics and Communication Engineering  
Coarse Grained Arrays (CGAs) with run-time re-configurability play a challenging task to design Network on-Chip (NoC) communication systems satisfying the power and area of embedded system.  ...  The proposed architecture is implemented on FPGA (Field Programmable Gate Array) using VHDL (VHSIC Hardware Description Language), and the obtained comparison power graph signifies that it consumes less  ...  The topology to interconnect cells in PE array is different. There are different types of topology used based on the application requirements.  ... 
doi:10.18831/ fatcat:jfgj5g733zbi5mgkfypfzvn6ga

Mapping of DSP Algorithms on Field Programmable Function Arrays [chapter]

Paul M. Heysters, Jaap Smit, Gerard J. M. Smit, Paul J. M. Havinga
2000 Lecture Notes in Computer Science  
A reconfigurable systems-architecture is introduced, with a focus on a Field Programmable Function Array (FPFA).  ...  Application domain specific algorithms determine the granularity of FPFA processor tiles. Several algorithms are discussed and mapped onto a FPFA processor tile.  ...  Figure 1 : FPFA architecture. The ALUs on a processor tile are tightly interconnected and are designed to execute the (highly regular) inner loops of an application domain.  ... 
doi:10.1007/3-540-44614-1_43 fatcat:2xtxzpsl7vf3bea2dmtprryrma

Design Methodology and Trade-Offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays

Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tanbunheng, Takuro Nakamura, Takashi Nishimura, Hideharu Amano
2007 2007 International Conference on Field Programmable Logic and Applications  
In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameterized.  ...  In our DRPA generator, although the fundamental design of a processing element (PE) and an inter-PE connection is fixed, the array size, PE granularity, and connection flexibilities of intra/inter PE are  ...  Acknowledgment This work is supported in part by Japan Science and Technology Agency(JST) and Japan Society for the Promotion of Science(JSPS).  ... 
doi:10.1109/fpl.2007.4380771 dblp:conf/fpl/HasegawaA07 fatcat:6rbshgl4nrhyrpynizzgbea56e
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