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A Reconfigurable FPGA System for Parallel Independent Component Analysis

Hongtao Du, Hairong Qi
2006 EURASIP Journal on Embedded Systems  
A run-time reconfigurable field programmable gate array (FPGA) system is presented for the implementation of the parallel independent component analysis (ICA) algorithm.  ...  Using the reconfigurability of FPGA, we show how to manipulate the FPGA-based system and execute processes for the parallel ICA (pICA) algorithm.  ...  CASE STUDY The validity of the developed reconfigurable FPGA system for the pICA algorithm is tested for the dimensionality reduction application in HSI analysis.  ... 
doi:10.1186/1687-3963-2006-023025 fatcat:xbog7yubvvg27m6q3exehbe72e

A Reconfigurable FPGA System for Parallel Independent Component Analysis

Hongtao Du, Hairong Qi
2006 EURASIP Journal on Embedded Systems  
A run-time reconfigurable field programmable gate array (FPGA) system is presented for the implementation of the parallel independent component analysis (ICA) algorithm.  ...  Using the reconfigurability of FPGA, we show how to manipulate the FPGA-based system and execute processes for the parallel ICA (pICA) algorithm.  ...  CASE STUDY The validity of the developed reconfigurable FPGA system for the pICA algorithm is tested for the dimensionality reduction application in HSI analysis.  ... 
doi:10.1155/es/2006/23025 fatcat:zlt3ppz54zfixmmdylsxkjvgty

Hardware Cost Analysis for Weakly Programmable Processor Arrays

Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jurgen Teich
2006 2006 International Symposium on System-on-Chip  
In this paper technology-independent hardware cost analysis for a new class of highly parameterizable coarse-grained reconfigurable architectures called weakly programmable processor arrays is performed  ...  Coarse-grained reconfigurable architectures support a high degree of parallelism at multiple levels.  ...  Modern hardware systems demand for a high level of reconfigurability and parallelism.  ... 
doi:10.1109/issoc.2006.321996 dblp:conf/issoc/KisslerHKT06 fatcat:ira6n7n3qfac7ib5j7vd7gszgm

Guest Editorial Note: Special Issue on Applied Reconfigurable Computing

Georgios Keramidas, Nikolaos Voros, Michael Huebner, Diana Goehringer
2020 Journal of Signal Processing Systems  
We hope that this special issue will serve as a valuable resource for the reconfigurable computing community.  ...  We would like to thank all the authors for their valuable contributions. Special thanks also to the researchers who contributed to the reviewing process.  ...  ReneGENE-GI proposes a dedicated acceleration fraemworks by exploiting the inherent parallelism and scalability of the reconfigurable hardware at the level of micro and system architecture.  ... 
doi:10.1007/s11265-020-01593-4 fatcat:nv3t6uhtk5foroxoxy3rdbqxeq

Integrating Reconfigurable Hardware-Based Grid for High Performance Computing

Julio Dondo Gazzano, Francisco Sanchez Molina, Fernando Rincon, Juan Carlos López
2015 The Scientific World Journal  
This work proposes a complete grid infrastructure for distributed high performance computing based on dynamically reconfigurable FPGAs.  ...  FPGAs have shown several characteristics that make them very attractive for high performance computing (HPC).  ...  Approaches for high performance reconfigurable computing (HPRC) integrate both processors and FPGAs into a parallel architecture.  ... 
doi:10.1155/2015/272536 pmid:25874241 pmcid:PMC4385699 fatcat:rrfxbkyrzfhu3df2qagz37vcle

A multiprocessor self-reconfigurable JPEG2000 encoder

Antonino Tumeo, Simone Borgio, Davide Bosisio, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
2009 2009 IEEE International Symposium on Parallel & Distributed Processing  
This paper presents a multiprocessor architecture prototype on a Field Programmable Gate Arrays (FPGA) with support for hardware and software multithreading.  ...  reconfiguration latency through the parallel execution of software threads.  ...  Our analysis concentrates on the two phases of the JPEG2000 for which we have parallel execution and the hardware implementation of the accelerators.  ... 
doi:10.1109/ipdps.2009.5161198 dblp:conf/ipps/TumeoBBMPFS09 fatcat:wwtmucew6rggzaj5ckejliavba

MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs

Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser
2008 2008 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia  
In this paper we present a novel SoC co-design methodology based on Model Driven Engineering using the MARTE (Modeling and Analysis of Real-time and Embedded Systems) standard.  ...  The goal is to carry out modeling at a high abstraction level expressed in UML (Unified Modeling Language) and following transformations of these models, automatically generate the code necessary for FPGA  ...  MARTE [3] (Modeling and Analysis of Real-Time and Embedded Systems) is an industry standard of the Object Management Group (OMG) for model-driven development of embedded systems and for SoC co-design  ... 
doi:10.1109/estmed.2008.4696994 dblp:conf/estimedia/QuadriMD08 fatcat:7dxo2e57cvh2ppwcnpeyp5hvkm

System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors

Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
2006 2006 International Conference on Computer Design  
In this paper, we propose a system-level energy estimation model to accompany our design methodology for HERA (HEterogeneous Reconfigurable Architecture), a versatile reconfigurable MPoPC that we have  ...  The model utilizes both physical-level measurements from a hardware component library and application statistics.  ...  We propose here a system-level, component-oriented energy estimation model for HERA which provides a quantitative basis for performance-energy trade-offs during system synthesis and runtime reconfiguration  ... 
doi:10.1109/iccd.2006.4380849 dblp:conf/iccd/WangZ06 fatcat:fkrzscizefc6rj6enuocn52qse

Energy-Aware Optimisation for Run-Time Reconfiguration

Tobias Becker, Wayne Luk, Peter Y. K. Cheung
2010 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines  
Based on this model, a method is introduced that establishes the optimal degree of parallelism for designs supporting partial run-time reconfiguration.  ...  a non-reconfigurable design.  ...  Previous work demonstrates that the degree of parallelism can be used to optimise the performance of a reconfigurable design [5] . We now perform a similar analysis for energy.  ... 
doi:10.1109/fccm.2010.17 dblp:conf/fccm/BeckerLC10 fatcat:qvpaxyc7gzc4djuj27jrumscxa

Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems

Pamela Wattebled, Jean-Philippe Diguet, Jean-Luc Dekeyser
2012 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)  
Partial and dynamic reconfiguration provides a relevant new dimension to design efficient parallel embedded systems.  ...  and its implementation for reconfigurable multiprocessor systems on dynamically reconfigurable circuits.  ...  concept for the design of HW components managing parallelism and dynamic reconfiguration.  ... 
doi:10.1109/recosoc.2012.6322884 dblp:conf/recosoc/WattebledDD12 fatcat:qxdiddqn5vayfofdagd6j5sovi

Multilevel Radiation Protection of Partially Reconfigurable Field Programmable Gate Array Devices

Lev Kirischian, Vadim Geurkov, Irina Terterian, Valeri Kirischian, Jacob Kleiman
2006 Journal of Spacecraft and Rockets  
Reconfigurable Parallel Stream Processing Platform FPGA under test SRAM Cache 4 SelectMAP FPGA XCVS50E } Hardware Operating System (HOS) b for VHC configuration it-streams ] | Logic Analyzer HP 54620C  ...  KIRISCHIAN ET Al TIT Wire LLL 6 — =) ace Reconfigurable Functional Module with the FPGA under test Hardware Operating System based on XCVS0E FPGA that contains cores of the self-restoration mechanism Parallel  ... 
doi:10.2514/1.15843 fatcat:whxx3zpgg5gg7jx3q6vnzyr2ge

High Performance Power Spectrum Analysis Using a FPGA Based Reconfigurable Computing Platform

Yogindra Abhyankar, C Sajish, Yogesh Agarwal, C.R. Subrahmanya, Peeyush Prasad
2006 2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006)  
In this paper, we present our design of a FPGA based reconfigurable platform for high performance power-spectrum analysis.  ...  Power-spectrum analysis is an important tool providing critical information about a signal. The range of applications includes communication-systems to DNA-sequencing.  ...  In Section 4 and 5, we discuss the scheme used for our implementation of power spectrum analysis on the FPGA based reconfigurable hardware and the experimental setup respectively.  ... 
doi:10.1109/reconf.2006.307786 dblp:conf/reconfig/AbhyankarSASP06 fatcat:y7hn3wih55eold5anqaxhpkuh4

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration

D. Pnevmatikatos, K. Papadimitriou, T. Becker, P. Böhm, A. Brokalakis, K. Bruneel, C. Ciobanu, T. Davidson, G. Gaydadjiev, K. Heyse, W. Luk, X. Niu (+9 others)
2015 Microprocessors and microsystems  
Our tool-chain supports both coarse-and fine-grain FPGA reconfiguration, while during execution a flexible run-time system manages the reconfigurable resources.  ...  The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) EU FP7 project, aims to ease the design and implementation of dynamically changing hardware systems.  ...  Fig. 8 . 8 System model showing the components of the run-time system. ) connected to the FPGA through a dedicated point-topoint link.  ... 
doi:10.1016/j.micpro.2014.09.006 fatcat:35jcur7nljhw7hqletmdrqjhum

An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing

Greg Stitt, Alan George, Herman Lam, Melissa Smith, Vikas Aggarwal, Gongyu Wang, Casey Reardon, Brian Holland, Seth Koehler, James Coole
2011 IEEE Design & Test of Computers  
Figure 5 . 5 ReCAP (Reconfigurable Computing Application Performance) performance analysis overview (a). Results for TDFIR showing poor scalability for original FPGA version (b).  ...  His research interests include high-performance architectures, networks, systems, services, and applications for reconfigurable, parallel, distributed, and fault-tolerant computing.  ... 
doi:10.1109/mdt.2011.46 fatcat:3ganqjg75jh3nanzr6obzc4xqq

Bridging parallel and reconfigurable computing with multilevel PGAS and SHMEM+

V. Aggarwal, A. George, K. Yalamanchili, C. Yoon, H. Lam, G. Stitt
2009 Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications - HPRCTA '09  
Reconfigurable computing (RC) systems based on FPGAs are becoming an increasingly attractive solution to building parallel systems of the future.  ...  Unlike traditional HPC systems, lack of integrated, system-wide, parallel-programming models and languages presents a significant design challenge for creating applications targeting scalable, reconfigurable  ...  The authors also thank Rafael Garcia, M.S. student, in our lab for his contributions to this work.  ... 
doi:10.1145/1646461.1646467 dblp:conf/sc/AggarwalGYYLS09 fatcat:q2mi2nwadzhwvmvfchk3oefqry
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