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A quasi-delay-insensitive method to overcome transistor variation

C. Brej, J.D. Garside
18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design  
This paper presents a method of overcoming these overheads to take full advantage of the improved manufacturing processes.  ...  Removing its timing assumptions allows a circuit to perform at a higher speed.  ...  Quasi-Delay-Insensitivity The Quasi Delay Insensitive (QDI) circuit class is almost as robust as DI. It admits isochronic forks [8] which allows the generation of computing circuits.  ... 
doi:10.1109/icvd.2005.30 dblp:conf/vlsid/BrejG05 fatcat:sl4fl5zttze23gkk3r7eotb5tu

Robust and Energy-Efficient Hardware: The Case for Asynchronous Design

Ney Laert Vilar Calazans, Taciano Ares Rodolfo, Marcos L. L. Sartori
2021 Journal of Integrated Circuits and Systems  
Asynchronous design and particularly quasi-delay insensitive design promises to deal with the same challenges more gracefully in current advanced nodes, and possibly irrevocably in future technology nodes  ...  In particular, the definition of a robust digital circuit comprises addressing several aspects to which a digital system design is expected to be robust to, including: (1) voltage variations; (2) process  ...  In fact, every time a reference above to the DI acronym appears, it refers to a type of code, while QDI (from quasi-delay insensitive) always refers to a class of circuit design techniques.  ... 
doi:10.29292/jics.v16i2.518 fatcat:3o2fynlz6rgrlg44dkz5jxp4dq

Efficient Realization of Strongly Indicating Function Blocks

P. Balasubramanian, D. A. Edwards
2008 2008 IEEE Computer Society Annual Symposium on VLSI  
Approximately 3 times reduction in transistor cost has been achieved by the proposed method in comparison with a recent work, based on analysis with benchmarks and widely used digital circuit functionality  ...  In this context, a novel design methodology for realizing non-regenerative logic as a function block, under the discipline of quasi-delayinsensitivity with four-phase handshaking and dualrail encoding,  ...  Circuits designed following the four-phase protocol dual-rail (DR) approach are generally quasi-delayinsensitive (QDI), since the class of delay-insensitive (DI) circuits is rather small [3] .  ... 
doi:10.1109/isvlsi.2008.103 dblp:conf/isvlsi/BalasubramanianE08 fatcat:lyw37jzb4zdvjhqlzjfesoll3m

The Design of High Performance Asynchronous Pipelines with Quasi Delay-Insensitive

D. Jayanthi, M. Rajaram
2012 International Journal of Computer Applications  
In this work, expose a timing assumption used in staticizers for QDI logic and apply it to other parts of circuits.  ...  The QDI templates are highly tolerant of process variations due to the up and down transitions are sensed. QDI circuits are quite robust in terms of process variations and design tolerances.  ...  Singlerail, in contrast, requires the associated request line, driven by a matched delay line, to always be longer than the computation.  ... 
doi:10.5120/8289-1862 fatcat:6dd47qtlznczbjvyrv725fnhka

Designing robust asynchronous circuit components

S. Mohammadi, S. Furber, J. Garside
2003 IEE Proceedings - Circuits Devices and Systems  
In addition, quasi-delay-insensitive circuits are based on the assumption of isochronic forks, an assumption that can in practice be compromised by threshold variations due to the use of, for example,  ...  A design methodology is proposed which overcomes the charge-sharing problem, resulting in more robust circuits.  ...  This method has a disadvantage: it increases the output capacitance and so the propagation delay of the gate.  ... 
doi:10.1049/ip-cds:20030349 fatcat:df6mlus4j5bwxnjmcjiipejvfu

Synthesis of PCHB-WCHB hybrid quasi-delay insensitive circuits

Chi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong R. Jiang
2014 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)  
Among various techniques, quasi-delay-insensitive (QDI) design is promising due to its very relaxed timing assumption.  ...  To overcome this obstacle, this paper proposes an efficient static performance analysis procedure and a synthesis flow for precharged half buffer (PCHB) and weak-conditioned half buffer (WCHB) circuit  ...  Quasi-Delay Insensitive Model The delay insensitive (DI) model makes no timing assumption on the gate and wire delays in a circuit, and is the most robust delay model in asynchronous design.  ... 
doi:10.1109/dac.2014.6881519 fatcat:pcylsvl7irbozm32chbnz7kqja

Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits

Chi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong R. Jiang
2014 Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14  
Among various techniques, quasi-delay-insensitive (QDI) design is promising due to its very relaxed timing assumption.  ...  To overcome this obstacle, this paper proposes an efficient static performance analysis procedure and a synthesis flow for precharged half buffer (PCHB) and weak-conditioned half buffer (WCHB) circuit  ...  Quasi-Delay Insensitive Model The delay insensitive (DI) model makes no timing assumption on the gate and wire delays in a circuit, and is the most robust delay model in asynchronous design.  ... 
doi:10.1145/2593069.2593224 dblp:conf/dac/ChuangLJ14 fatcat:uafzc2vcffh53geaqy7deioalm

Hardware Trojan detection in soft error tolerant macro synchronous micro asynchronous (MSMA) pipeline

Faiq Khalid Lodhi, Syed Rafay Hasan, Osman Hasan, Falah Awwad
2014 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)  
Recently, low power quasi delay insensitive (QDI) null conventional logic based asynchronous circuits have been proposed, but these circuits work for pure asynchronous designs only.  ...  This paper provides a proof of concept soft error tolerant MSMA design. Time delay based signature without using clock distribution network is obtained to detect hardware Trojan insertion in MSMA.  ...  Due to the inherent error detection capability of quasi delay insensitive (QDI) asynchronous circuits, researchers explored them for the prevention and detection of soft errors.  ... 
doi:10.1109/mwscas.2014.6908501 dblp:conf/mwscas/LodhiHHA14 fatcat:3iwag7rcs5egjeojkhlihbjxkq

TDTB error detecting latches: Timing violation sensitivity analysis and optimization

Matheus T. Moreira, Dylan Hand, Peter A. Beerel, Ney L. V. Calazans
2015 Sixteenth International Symposium on Quality Electronic Design  
To overcome this limitation, we propose transistor level optimizations that enable safe operation, guaranteeing that all timing violations are captured, for a cost of 3 extra transistors, 30% in leakage  ...  Increasing process variations and sensitivity to operating conditions are making the design of traditional synchronous circuits a challenging task.  ...  These optimizations rely on both transistor sizing and classic asynchronous design techniques that known for long by quasi-delay-insensitive designers.  ... 
doi:10.1109/isqed.2015.7085455 dblp:conf/isqed/MoreiraHBC15 fatcat:su6dswy2zfahbcstybjzncf72a

Enhancing Side Channel Attack-Resistance of the STTL Combining Multi-Vt Transistors with Capacitance and Current Paths Counterbalancing

Vitor Gonçalves Lima, Guilherme Paim, Rodrigo Wuerdig, Leandro Mateus Giacomini Rocha, Leomar Da Rosa Júnior, Felipe Marques, Vinicius Valduga, Eduardo Costa, Rafael Soares, Sergio Bampi
2020 Journal of Integrated Circuits and Systems  
STTL is robust to attacks due to the delay in an insensitive feature that mitigates the logic glitches generated by the different path delays that lead to the logic gate inputs until they stabilize.  ...  Our work proposes three circuit topologies, combining multi-Vt transistors with a circuit counterbalancing strategy, aiming to improve the STTL DPA attack-resistance.  ...  Rocha would like to thank the IFRS for his temporary license to pursuing the Ph.D. with full-time dedication.  ... 
doi:10.29292/jics.v15i1.100 fatcat:gi4ftsujzrbxle46pzbl3knrqa

Comparative evaluation of quasi-delay-insensitive asynchronous adders corresponding to return-to-zero and return-to-one handshaking

Padmanabhan Balasubramanian
2018 Facta universitatis - series Electronics and Energetics  
This article makes a comparative evaluation of quasi-delay-insensitive (QDI) asynchronous adders, realized using the delay-insensitive dual-rail code, which adhere to 4-phase return-to-zero (RTZ) and 4  ...  The QDI adders correspond to three different timing regimes viz. strong-indication, weak-indication, and early output. They are physically implemented using a 32/28nm CMOS process.  ...  weakest compromise to delay-insensitivity.  ... 
doi:10.2298/fuee1801025b fatcat:l5i6rz3gp5d3titjxmj7acgmkq

Energy Efficient Mobile Service Computing with Differential Spintronic-C-elements: A Logic-in-Memory Asynchronous Computing Paradigm

Ashkan Samiee, Yunchuan Sun, Ronald DeMara, Yoonsuk Choi, Yu Bai
2019 IEEE Access  
The experimental results show that the asynchronous processors attain a four-fold throughput increase relative to their synchronous counterparts under these operating constraints.  ...  The results indicate that the proposed design achieves 38% leakage reduction and 30% accuracy improvement compared to the state-of-the-art non-volatile asynchronous circuits.  ...  NON-VOLATILE ASYNCHRONOUS CIRCUITS DESIGNS To illustrate the benefits of NV functionality, a Quasi Delay Insensitive (QDI) asynchronous pipeline is chosen which is equipped with a dual rail 4-phase handshake  ... 
doi:10.1109/access.2019.2911098 fatcat:fs5xujbdxvhz5biggjm6qmi7yy

Low Power Sub Threshold QDI Kogge Stone Adder using Sense Amplifier Lector based Half Buffer Cell Templates

2019 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
A 16-piece Kogge Stone Adder (KSA) is structured and actualized utilizing an asynchronous Quasi-Delay-Insensitive cell configuration approach known as the SALHB algorithm.  ...  Hence, SALHB method was proposed to overcome the problem of high leakage current.  ...  In the proposed method, we embed two leakage control transistors (a p-type and a n-type) between draw up and pull-down system of the rationale gate in which the source terminal of one transistor controls  ... 
doi:10.35940/ijitee.k1028.09811s219 fatcat:jht2hhbwqreujeimv524dmcasy

Asynchronous design methodologies: an overview

S. Hauck
1995 Proceedings of the IEEE  
Automatic adaptation to physical properties -The delay through a circuit can change with variations in fabrication, temperature, and power-supply voltage.  ...  quasidelay-insensitive circuits.  ...  Acknowledgments This paper has been greatly improved by a number of patient readers, including Gaetano Borriello, John Brzozowski, Al Davis, David Dill, Carl Ebeling, Jo Ebergen, Henrik Hulgaard, Carl  ... 
doi:10.1109/5.362752 fatcat:2wtrcnhd3beeve2vzcuij6vydq

TITAC: design of a quasi-delay-insensitive microprocessor

T. Nanya, Y. Ueno, H. Kagotani, M. Kuwako, A. Takamura
1994 IEEE Design & Test of Computers  
e sign based on the quasi-delay-insensitive model.  ...  major issue in delayinsensitive or quasi-delay-insensitive processor design.  ...  He is a senior member of the IEEE and a member of the Computer Society. Yoichiro Ueno is working toward a Dr.  ... 
doi:10.1109/54.282445 fatcat:xhil6kqdonhthbdz7phps2ohmy
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