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A Predictable Communication Scheme for Embedded Multiprocessor Systems

Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici
2006 2006 IFIP International Conference on Very Large Scale Integration  
A dynamic allocation is more suitable for flexible multiprocessor systems and requires the implementation of a Quality-of-Service (QoS) mechanism.  ...  This paper explores the main QoS schemes suitable for such systems: connection-oriented and connectionless.  ...  CONCLUSIONS The present work contrasts two techniques which dynamically allocate communication resources to improve on-chip predictability in a flexible multiprocessor system.  ... 
doi:10.1109/vlsisoc.2006.313225 dblp:conf/vlsi/HarmanciPIL06 fatcat:alpas2gl4jgm3c5vdx7akcklya

Online Adaptive Fault Tolerant based Feedback Control Scheduling Algorithm for Multiprocessor Embedded Systems [article]

Oumair Naseer, Rana Atif Ali Khan
2012 arXiv   pre-print
This procedure is important for control scheduling co-design for multiprocessor embedded systems.  ...  This paper presented a novel methodology of designing an online adaptive fault tolerant based feedback control algorithm for multiprocessor embedded systems.  ...  Integrated Fault tolerance scheme check-pointing for real time embedded systems is presented in [7] .  ... 
arXiv:1210.2882v1 fatcat:bjzdz572dvaqtjj7opsgngu25q

Online Adaptive Fault Tolerant Based Feedback Control Scheduling Algorithm for Multiprocessor Embedded Systems

Oumair Naseer
2012 International Journal of Embedded Systems and Applications  
This procedure is important for control scheduling codesign for multiprocessor embedded systems.  ...  This paper presented a novel methodology of designing an online adaptive fault tolerant based feedback control algorithm for multiprocessor embedded systems.  ...  Integrated Fault tolerance scheme check-pointing for real time embedded systems is presented in [7] .  ... 
doi:10.5121/ijesa.2012.2301 fatcat:xr4w35hg3rcyjlwrxfbkyt7u6m

Towards a Java multiprocessor

Christof Pitter, Martin Schoeberl
2007 Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems - JTRES '07  
This paper describes the first steps towards a Java multiprocessor system on a single chip for embedded systems.  ...  The proposed memory arbiter resolves possible emerging conflicts of parallel accesses to the shared memory using a fixed priority scheme. Furthermore, the paper describes the boot-up of the CMP.  ...  Acknowledgement The TPCM-project received support from the Austrian FIT-IT SoC initiative, funded by the Austrian Ministry for Traffic, Innovation and Technology (BMVIT) and managed by the Austrian Research  ... 
doi:10.1145/1288940.1288962 dblp:conf/jtres/PitterS07 fatcat:kymjieugtfg4va4l375ek256ue

Predictable Embedded Multiprocessor System Design [chapter]

Marco Bekooij, Orlando Moreira, Peter Poplavko, Bart Mesman, Milan Pastrnak, Jef van Meerbergen
2004 Lecture Notes in Computer Science  
Predictable heterogenous application domain specific multiprocessor systems, which are designed around networks-on-chip, can meet demanding performance, flexibility and power-efficiency requirements as  ...  A traditional implementation of a predictable multiprocessor system for channel decoding and video processing is a pipe of tighly coupled dedicated hardware blocks with some glue logic for the communication  ...  An example of a predictable arbitration scheme for a bus is Time Division Multiple Access (TDMA).  ... 
doi:10.1007/978-3-540-30113-4_7 fatcat:euzbagceuvfqrfjmnqyzn57qmq

A Resolution for Shared Memory Conflict in Multiprocessor System-on-a-Chip [article]

Shaily Mittal, Nitin
2012 arXiv   pre-print
Now days, manufacturers are focusing on increasing the concurrency in multiprocessor system-on-a-chip (MPSoC) architecture instead of increasing clock speed, for embedded systems.  ...  In this paper, we propose a new semaphore scheme for synchronization in shared cache memory in an MPSoC.  ...  The multiprocessor System-on-a-chip (MPSoC) [2] is a system-on-a-chip (SoC) which has multiple processors on a single chip, generally used for embedded applications.  ... 
arXiv:1202.0613v1 fatcat:27ky77b3nrgj3g6eupgkitblwq

Supporting Task Migration in Multi-Processor Systems-on-Chip: A Feasibility Study

S. Bertozzi, A. Acquaviva, D. Bertozzi, A. Poggiali
2006 Proceedings of the Design Automation & Test in Europe Conference  
Our paper proposes a task management software infrastructure that is well suited for the constraints of single chip multiprocessors with distributed operating systems.  ...  In order to prove the practical viability of this scheme, we also propose a characterization methodology for task migration overhead.  ...  This cost could be critical in an embedded MPSoC system, specially if it is not predictable. For this reason, we propose a lightweight migration support that is more suitable to embedded systems.  ... 
doi:10.1109/date.2006.243952 dblp:conf/date/BertozziABP06 fatcat:ir54llwkwfafhhd6ucczwq7jpq

Toward embedded qualitative simulation: a specialized computer architecture for QSim

M. Platzner, B. Rinner, R. Weiss
2000 IEEE Intelligent Systems and their Applications  
To demonstrate our approach's suitability for embedded qualitative simulation, we have developed a prototype implementation on a heterogeneous multiprocessor system.  ...  to embedded computer platforms.  ...  Acknowledgments This work took place at the Institute for Technical Informatics, Technical University Graz, and was supported by the Austrian Science Fund under grants P10411-MAT and J1429-MAT.  ... 
doi:10.1109/5254.850829 fatcat:aqzpsj2nlbhyxdd2eobtrev5ke

System-level performance analysis of multiprocessor system-on-chips by combining analytical model and execution time variation

Sungchan Kim, Soonhoi Ha
2014 Microprocessors and microsystems  
As the impact of the communication architecture on performance grows in a Multiprocessor Systemon-Chip (MPSoC) design, the need for performance analysis in the early stage in order to consider various  ...  In this paper, we propose a novel system-level performance analysis method to estimate the performance distribution of an MPSoC.  ...  Such a chip, which uses multiple processors, is called a Multiprocessor System-on-Chip (MPSoC).  ... 
doi:10.1016/j.micpro.2014.02.003 fatcat:wsonxvepd5gfthhxp5ehlebrma

Design and implementation of embedded multiprocessor architecture using FPGA

Muataz H. Salih, M. R. Arshad
2010 2010 IEEE Symposium on Industrial Electronics and Applications (ISIEA)  
This paper proposes a design and implementation of embedded multiprocessors architecture system focusing on its design area and performance.  ...  Modern embedded multiprocessors are complex systems that often require years to design and verify.  ...  Acknowledgments The authors would like to thank the Underwater Robotics Research Group (URRG) in the USM for their assistance and NOD, MOSTI, for providing the research grant (Grant no. 6050124).  ... 
doi:10.1109/isiea.2010.5679397 fatcat:srjvmfyhrbafri5onb2gdmkpbq

A real-time Java chip-multiprocessor

Christof Pitter, Martin Schoeberl
2010 ACM Transactions on Embedded Computing Systems  
Chip-multiprocessors are an emerging trend for embedded systems. In this paper, we introduce a real-time Java multiprocessor called JopCMP.  ...  Our research shows that timing analysis is in fact possible for homogeneous multiprocessor systems with a shared memory.  ...  This processor has been designed from scratch to provide a time-predictable execution environment for embedded real-time systems.  ... 
doi:10.1145/1814539.1814548 fatcat:zcki425nfndqtjmloz2sdi4eei

An optimized message passing framework for parallel implementation of signal processing applications

Sankalita Saha, Jason Schlessman, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Wayne Wolf
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
One of the most significant challenges is communication between the various computing elements for parallel implementation.  ...  SPI is targeted towards signal processing applications and, due to its careful specialization, more performance-efficient for their embedded implementation.  ...  separation between communication and computation for easier development of embedded multiprocessor systems.  ... 
doi:10.1145/1403375.1403671 fatcat:balkvrrbw5fptl2j5sr5s626u4

An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications

Sankalita Saha, Jason Schlessman, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Wayne Wolf
2008 2008 Design, Automation and Test in Europe  
One of the most significant challenges is communication between the various computing elements for parallel implementation.  ...  SPI is targeted towards signal processing applications and, due to its careful specialization, more performance-efficient for their embedded implementation.  ...  separation between communication and computation for easier development of embedded multiprocessor systems.  ... 
doi:10.1109/date.2008.4484845 dblp:conf/date/SahaSPBW08 fatcat:33jpzxk6nfd7zntbcqktb4faw4

An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography

Xinyu Li, Omar Hammami
2009 International Journal of Reconfigurable Computing  
Embedded system design is increasingly based on single chip multiprocessors because of the high performance and flexibility requirements.  ...  And the overall multiprocessor architecture is still kept for additional applications. This provides a transition to software only parallel implementation while avoiding pure hardware implementation.  ...  This helps to better tune embedded system and offer Paretolike choices of configurations for system designers.  ... 
doi:10.1155/2009/631490 fatcat:kcrbtxmc7jgd3jptwwrxqcuqf4

Application Specific Customization and Scalability of Soft Multiprocessors

Deepak Unnikrishnan, Jia Zhao, Russell Tessier
2009 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines  
In the future, we plan to improve our soft multiprocessor systems by supporting advanced features such as off-chip memory accesses and better branch prediction schemes.  ...  Some of the other limitations include a lack of support for dynamic branch predictions, exceptions and operating systems.  ... 
doi:10.1109/fccm.2009.41 dblp:conf/fccm/UnnikrishnanZT09 fatcat:7cjy7ltl4rcyzlo7e2p4hdecdq
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