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A pipelined memory architecture for high throughput network processors

Timothy Sherwood, George Varghese, Brad Calder
2003 Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03  
We propose a pipelined memory design that emphasizes worst-case throughput over latency, and co-explore architectural tradeoffs with the design of several important network algorithms.  ...  In this paper we focus on the design of a programmable architecture for backbone routers, based on the manipulation of wide irregular memory words, that can provide a feasible design alternative to custom  ...  ANI-0074004, a grant from NIST on the Sensilla Project, and a grant from Intel.  ... 
doi:10.1145/859651.859652 fatcat:s6t7kqxhmnggjisfueguwgfyke

A pipelined memory architecture for high throughput network processors

Timothy Sherwood, George Varghese, Brad Calder
2003 Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03  
We propose a pipelined memory design that emphasizes worst-case throughput over latency, and co-explore architectural tradeoffs with the design of several important network algorithms.  ...  In this paper we focus on the design of a programmable architecture for backbone routers, based on the manipulation of wide irregular memory words, that can provide a feasible design alternative to custom  ...  ANI-0074004, a grant from NIST on the Sensilla Project, and a grant from Intel.  ... 
doi:10.1145/859618.859652 fatcat:gqbkgwedrjd6lhfdut3wyaqhre

A pipelined memory architecture for high throughput network processors

Timothy Sherwood, George Varghese, Brad Calder
2003 SIGARCH Computer Architecture News  
We propose a pipelined memory design that emphasizes worst-case throughput over latency, and co-explore architectural tradeoffs with the design of several important network algorithms.  ...  In this paper we focus on the design of a programmable architecture for backbone routers, based on the manipulation of wide irregular memory words, that can provide a feasible design alternative to custom  ...  ANI-0074004, a grant from NIST on the Sensilla Project, and a grant from Intel.  ... 
doi:10.1145/871656.859652 fatcat:bjx7au4rrvdb7fymgiedanp25m

A pipelined memory architecture for high throughput network processors

T. Sherwood, G. Varghese, B. Calder
30th Annual International Symposium on Computer Architecture, 2003. Proceedings.  
We propose a pipelined memory design that emphasizes worst-case throughput over latency, and co-explore architectural tradeoffs with the design of several important network algorithms.  ...  In this paper we focus on the design of a programmable architecture for backbone routers, based on the manipulation of wide irregular memory words, that can provide a feasible design alternative to custom  ...  ANI-0074004, a grant from NIST on the Sensilla Project, and a grant from Intel.  ... 
doi:10.1109/isca.2003.1207008 dblp:conf/isca/SherwoodVC03 fatcat:7lwqkhax35e5zhgferbkfnehg4

Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing

Aydin O. Balkan, Michael N. Horak, Gang Qu, Uzi Vishkin
2007 15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007)  
A Mesh of Trees (MoT) on-chip interconnection network has been proposed recently to provide high throughput between memory units and processors for single-chip parallel processing [5] .  ...  In that context, a 32-terminal MoT network could support up to 512 on-chip XMT processors.  ...  Similarly, a more recent on-chip network [3] could provide high performance for local traffic, when processors have private caches and there are only a few globally shared memory units.  ... 
doi:10.1109/hoti.2007.4296804 fatcat:gwdxnmflpjeoxh6b2tfzvuncfu

Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing

Aydin O. Balkan, Michael N. Horak, Gang Qu, Uzi Vishkin
2007 15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007)  
A Mesh of Trees (MoT) on-chip interconnection network has been proposed recently to provide high throughput between memory units and processors for single-chip parallel processing [5] .  ...  In that context, a 32-terminal MoT network could support up to 512 on-chip XMT processors.  ...  Similarly, a more recent on-chip network [3] could provide high performance for local traffic, when processors have private caches and there are only a few globally shared memory units.  ... 
doi:10.1109/hoti.2007.11 dblp:conf/hoti/BalkanHQV07 fatcat:hqqqrfxlhfd5pnreeab66wrul4

Design of interleaved multithreading for Network Processors on Chip

H.C. Freitas, F.L. Madruga, M. Alves, P. Navaux
2009 2009 IEEE International Symposium on Circuits and Systems  
In the same way, Networks-on-Chip (NoCs) are the main alternatives for supporting packet throughput for the next generations of many-core processors.  ...  NPoC (Network Processor on Chip) is a proposal to increase the performance of programmable NoC routers and multi-cluster NoC architectures using Interleaved Multithreading (IMT) technique.  ...  In common architectures without multithreading support, there is a high latency to switch thread context between register bank and memory.  ... 
doi:10.1109/iscas.2009.5118237 dblp:conf/iscas/FreitasMAN09 fatcat:zgromdz24bfhxnfltptrjxcth4

Page 12 of Computer Performance Vol. 5, Issue 2 [page]

1984 Computer Performance  
If all possible architectures with n PEs are compared, the pipeline computer has a slightly higher throughput at a reduced cost, although its reliability is no better than any other processor architecture  ...  A CPS with a high quality, reliable and fault- tolerent pipeline computer represents the most advantageous and cost effective method of routing a steady flow of messages at any network node.  ... 

Gigabit routing on a software-exposed tiled-microprocessor

Umar Saif, James W. Anderson, Anthony Degangi, Anant Agarwal
2005 Proceedings of the 2005 symposium on Architecture for networking and communications systems - ANCS '05  
This paper investigates the suitability of emerging tiled-architectures, equipped with low-latency on-chip networks, for high-performance network routing.  ...  faster than Intel's IXP1200 Network Processor.  ...  a pipeline of processors.  ... 
doi:10.1145/1095890.1095899 dblp:conf/ancs/SaifADA05 fatcat:yrtvw4uk2baohn6s6txclxt2zu

A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications

Minhyeok Shin, Hanho Lee
2008 2008 IEEE International Symposium on Circuits and Systems  
In this paper, we present a novel high-speed lowcomplexity four data-path 128-point radix-2 4 FFT/IFFT processor for high-throughput MB-OFDM UWB systems.  ...  The high radix radix-2 4 multi-path delay feed-back (MDF) FFT architecture provides a higher throughput rate and low hardware complexity by using a four-parallel data-path scheme.  ...  This paper proposes a high-speed low-complexity four-parallel radix-2 4 FFT/IFFT processor with a fourparallel data-path pipelined architecture and a multi-path delay feed-back (MDF) structure to address  ... 
doi:10.1109/iscas.2008.4541579 dblp:conf/iscas/ShinL08 fatcat:suvffhjrczeedfyn7c2k3dhc4m

Datarol-II: A fine-grain massively parallel architecture [chapter]

Tetsuo Kawano, Shigeru Kusakabe, Rin-ichiro Taniguchi, Makoto Amamiya
1994 Lecture Notes in Computer Science  
The simulation results show that the Datarol-II processor can tolerate remote memory access latencies and execute a fine-grain multi-thread program efficiently.  ...  A two-level hierarchical memory system is also introduced in order to reduce memory access latency.  ...  In addition, a high speed memory, called Register Buffer (RB), is introduced in MU to reduce memory access time.  ... 
doi:10.1007/3-540-58184-7_156 fatcat:thh3ez4jlrfh3ghdvj73n6ctoq

Low-Power, Real-Time Object-Recognition Processors for Mobile Vision Systems

Jinwook Oh, Gyeonghoon Kim, Injoon Hong, Junyoung Park, Seungjin Lee, Joo-Young Kim, Jeong-Ho Woo, Hoi-Jun Yoo
2012 IEEE Micro  
for energy efficiency, a heterogeneous multicore architecture for data and thread parallelism, and network-on-chip (NoC) communications for high bandwidth.  ...  on high memory locality.  ... 
doi:10.1109/mm.2012.90 fatcat:e6st56neobcy3fho2fipizqzkq

Performances of multiprocessor multidisk architectures for continuous media storage

Benoit A. Gennart, Vincent Messerli, Roger D. Hersch, Ishwar K. Sethi, Ramesh C. Jain
1996 Storage and Retrieval for Still Image and Video Databases IV  
The results suggest that the shared bus is a potential bottleneck despite its very high hardware throughput (400Mbytes/s) and that an architecture with addressable local memories located closely to their  ...  The point-to-point architecture is scalable and able to sustain high throughputs for simultaneous compute-bound and data-bound operations.  ...  The RAID-II architecture approach 1 oers high-bandwidth disk arrays hooked directly onto high-speed networks.  ... 
doi:10.1117/12.234806 dblp:conf/spieSR/GennartMH96 fatcat:4k2pjsxt45dmdclhumhheco6sa

SODA

Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Krisztian Flautner
2006 SIGARCH Computer Architecture News  
The basic processing element is an asymmetric processor consisting of a scalar and SIMD pipeline, and a set of distributed scratchpad memories that are fully managed in software.  ...  In this paper, we present a design study for a fully programmable architecture, SODA, that supports software defined radio -a high-end signal processing application.  ...  Similar to the SODA architecture, each Sandblaster processor consists of a scalar processor and a high throughput vector processing unit.  ... 
doi:10.1145/1150019.1136494 fatcat:eual6romzfd7neirdqmkne5tai

A 128-Point FFT/IFFT Processor for MIMO-OFDM Transceivers – a Broader Survey

Devi Vasumathy N., Vigneswaran T.
2016 International Journal of Engineering and Technology  
This architecture has high throughput but worst hardware efficiency.  ...  In the MIMO OFDM transceiver, the fast Fourier transform (FFT) processor is a key component with high computational complexity.  ...  The FFT architecture that uses multiple data paths and feedback memory achieve high data throughput with less hardware complexity.  ... 
doi:10.21817/ijet/2016/v8i5/160805435 fatcat:r6bhs4w6dnh6nd33yzyqsk5i7i
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