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Fpga Design For H.264/Avc Encoder

A. Ben Atitallah, H. Loukil, N. Masmoudi
2011 Zenodo  
The throughput of the FPGA architecture reaches a processing rate higher than 177 million of pixels per second at 130 MHz, permitting its use in H.264/AVC standard directed to HDTV.  ...  In this paper, we describe an FPGA H.264/AVC encoder architecture performing at real-time.  ...  H.264/AVC FPGA architecture in term of the number of hardware cycles.  ... 
doi:10.5281/zenodo.1254922 fatcat:gvu33b6hbng35fkelg7qdi3jgi

Parallel deblocking filter for H.264 AVC/SVC

S Vijay, C Chakrabarti, L J Karam
2010 2010 IEEE Workshop On Signal Processing Systems  
This paper presents a parallel and scalable solution for adaptive deblocking filtering in H.264/AVC.  ...  A dedicated hardware architecture to process 2 edges is presented along with synthesis results.  ...  INTRODUCTION The H.264/AVC is the newest video coding standard of Joint Video Team (JVT) [1] that is widely used in video communication servers in network and wireless environment [2] - [3] .  ... 
doi:10.1109/sips.2010.5624773 fatcat:63mdnd2rzjbkfb262ah6exbfvq

H.264/AVC baseline profile decoder complexity analysis

M. Horowitz, A. Joch, F. Kossentini, A. Hallapuro
2003 IEEE transactions on circuits and systems for video technology (Print)  
In this paper, we study and analyze the computational complexity of a software-based H.264/AVC baseline profile decoder.  ...  Using the measured frequencies, estimates of the decoder time complexity for various hardware platforms can be determined.  ...  frequencies can be used to estimate the H.264/AVC baseline decoder time complexity for various hardware platforms.  ... 
doi:10.1109/tcsvt.2003.814967 fatcat:iusuhimevvdihay7flxrzarkie

A Bit-Serial Architecture For H.264/Avc Interframe Ddecoding

Paweł Garstecki, Adam Luczak, Tomasz Zernicki
2006 Zenodo  
Publication in the conference proceedings of EUSIPCO, Florence, Italy, 2006  ...  Therefore, it is the main part of this paper. THE H.264/AVC INTER PREDICTION The H.264/AVC inter prediction can be invoked in four main modes: Inter16x16, Inter16x8, Inter8x16 and Inter8x8.  ...  Interpolation of chrominance samples is carried out within 16 clock cycles. CONCLUSIONS Original architecture of inter prediction block for H.264/AVC decoder has been presented.  ... 
doi:10.5281/zenodo.52819 fatcat:dnz2itragvb2plthkvi2mgeuuq

Hardware architecture design of an H.264/AVC video codec

Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
This paper describes the design methodology for H.264/AVC video codec. The system architecture and scheduling will be addressed.  ...  H.264/AVC is the latest video coding standard.  ...  H.264/AVC ENCODING SYSTEM This section describes a new MB pipelining scheme for H.264/AVC encoder.  ... 
doi:10.1145/1118299.1118473 fatcat:i7xscbbjvbew3jlmjda3cwhqky

Algorithms and DSP implementation of H.264/AVC

Hung-Chih Lin, Yu-Jen Wang, Kai-Ting Cheng, Shang-Yu Yeh, Wei-Nien Chen, Chia-Yang Tsai, Tian-Sheuan Chang, Hsueh-Ming Hang
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
This survey paper intends to provide a comprehensive coverage of the techniques that are pertinent to the processor-based implementation of H.264/AVC video codec, particularly on DSP.  ...  Fast algorithms for motion estimation, intra-prediction and mode decision are described to reduce the computational complexity.  ...  Conclusions H.264/AVC is an efficient video compression scheme but this codec, particularly the encoder, has a very high computational complexity.  ... 
doi:10.1145/1118299.1118472 fatcat:dlecsrq3svbbnepvmg653xn6ci

Motion Estimation for H.264/AVC using Programmable Graphics Hardware

Chi-wang Ho, Oscar Au, S.-h. Chan, Shu-kei Yip, Hoi-ming Wong
2006 2006 IEEE International Conference on Multimedia and Expo  
We present an efficient implementation of motion estimation (ME) for H.264/AVC using programmable graphics hardware.  ...  The cost function for ME in H.264/AVC depends on the motion vector (MV) predictor which is the median MV of three neighboring coded blocks.  ...  GHP/033/05) and Research Grants Council (DAG04/05.EG34) of the Hong Kong Special Administrative Region, China.  ... 
doi:10.1109/icme.2006.262617 dblp:conf/icmcs/HoACYW06 fatcat:nksgchkflfgrbfoz2ymiznbpri

VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC

Yi-Hau Chen, Tung-Chien Chen, Shao-Yi Chien, Yu-Wen Huang, Liang-Gee Chen
2008 Journal of Signal Processing Systems  
The H.264/AVC Fractional Motion Estimation (FME) with rate-distortion constrained mode decision can improve the rate-distortion efficiency by 2-6 dB in peak signal-to-noise ratio.  ...  Acceleration by dedicated hardware is a must for real-time applications.  ...  Several fast algorithms and hardware architectures are proposed for H.264/AVC IME [6] [7] [8] [9] , but not for FME.  ... 
doi:10.1007/s11265-008-0213-7 fatcat:vj523iqj3rfijogrnpjkgvjdiq

A Novel Spiral-Type Motion Estimation Architecture for H.264/AVC

Naoyuki Hirai, Tian Song, Yizhong Liu, Takashi Shimamoto
2010 JSTS Journal of Semiconductor Technology and Science  
New features of motion compensation, such as variable block size and multiple reference frames are introduced in H.264/AVC.  ...  In this paper, an efficient architecture for spiral-type motion estimation is proposed. First, we propose a hardware-friendly spiral search order.  ...  MOTION ESTIMATION OF H.264/AVC In H.264/AVC, several new technologies such as VBSME, multiple frame motion estimation, and sub-pixel motion estimation are introduced.  ... 
doi:10.5573/jsts.2010.10.1.037 fatcat:l2tvi7jt5vblvb2cawqdktojgi

Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding

Ke Xu, Tsu-Ming Liu, Jiun-In Guo, Chiu-Sing Choy
2009 Journal of Signal Processing Systems  
This paper presents methods for efficient optimization of ASIC implementation for H.264/AVC video decoding. A systematic approach in optimization is presented in a top-down flow.  ...  The system architecture is first evaluated. We then focus on the pipeline organization, parallelism, and memory architecture optimization.  ...  A hybrid pipeline architecture that adopts different pipeline granularities for various coding tools is first proposed in [19] and gradually becomes the dominant pipelining architecture for H.264/AVC  ... 
doi:10.1007/s11265-009-0408-6 fatcat:dhvbpcut5bgonhbe5y2dbetc5m

H.264/AVC framework for multi-core embedded video encoders

Tiago Dias, Nuno Roma, Leonel Sousa
2010 2010 International Symposium on System on Chip  
A highly modular framework for developing parallel H.264/AVC video encoders in multi-core systems is presented.  ...  To prove the validity of the proposed framework, an implementation of a multicore H.264/AVC video encoder using an ASIP IP core as a ME hardware accelerator is presented.  ...  As Fig. 1 illustrates, the proposed SoC also uses a specialized processor to speedup the Motion Estimation (ME) operation, which is reported in literature as the most complex operation of a H.264/AVC  ... 
doi:10.1109/issoc.2010.5625538 dblp:conf/issoc/DiasRS10 fatcat:6dtcwebrxvfxdmae2z2bzdhgpm

FPGA Based Architectures for H. 264/AVC Video Compression Standard

Luciano Agostini, Sergio Bampi
2006 2006 International Conference on Field Programmable Logic and Applications  
Keywords −− H.264/AVC video compression, dedicated hardware for video compression, 2-D FDCT, 2-D IDCT, integer transforms.  ...  This paper presents the architecture and the VHDL design of the integer Two-Dimensional Discrete Cosine Transform (2-D DCT) used in the H.264/AVC codecs.  ...  RELATED WORKS There are a few papers in the literature about dedicated hardware architectures for H.264/AVC transforms.  ... 
doi:10.1109/fpl.2006.311361 dblp:conf/fpl/AgostiniB06 fatcat:ikeee2a6f5bqdobe7mgcb2rba4

Adaptive Computationally Scalable Motion Estimation for the Hardware H.264/AVC Encoder

Grzegorz Pastuszak, Mariusz Jakubowski
2013 IEEE transactions on circuits and systems for video technology (Print)  
Index Terms-Field-programmable gate array (FPGA), H.264/AVC, motion estimation, very large-scale integration (VLSI) architecture, video coding.  ...  The adaptive computationally scalable motion-estimation algorithm and its hardware implementation described in this paper allow the H.264/AVC encoders to achieve efficiencies close to optimal in real-time  ...  Therefore, similarly to the fast full search adopted in the JM H.264/AVC reference software [15], each SP is checked for all modes in parallel.  ... 
doi:10.1109/tcsvt.2012.2223791 fatcat:kqmp7ycmovcibh45nhbgy5vney

Low-power, high-throughput deblocking filter for H.264/AVC

Muhammad Nadeem, Stephan Wong, Georgi Kuzmanov, Ahsan Shabbir, Muhammad Faisal Nadeem, Fakhar Anjam
2010 2010 International Symposium on System on Chip  
In this paper, we present a low-power, high-throughput hardware implementation of deblocking filter core in H.264/AVC for battery-powered multimedia electronic devices.  ...  The hardware implementation is based an optimized deblocking filter algorithm with 50% less number of addition operations.  ...  [15] also proposed a low-power, high-throughput 4-stage pipelined architecture, implemented using 0.18 μm CMOS standard cell technology, for deblocking filter in H.264/AVC.  ... 
doi:10.1109/issoc.2010.5625535 dblp:conf/issoc/NadeemWKSNA10 fatcat:bk55hyyhizeqvcxii5fyjfklqe

A VLSI Architecture for H.264/AVC Variable Block Size Motion Estimation

Dam. Minh Tung, Tran. Le Thang Dong
2015 Journal of Automation and Control Engineering  
In this paper, we propose an efficient VLSI architecture for variable block size motion estimation (VBSME) in H.264/AVC to reduce the hardware cost and latency.  ...  The proposed architecture adopts four modes (8x8, 8x16, 16x8 and 16x16 modes) instead of seven modes for VBSME specified in H.264/AVC.  ...  Therefore, it may limit the performance of the BMA for low bit rate video coding applications. Manuscript H.264/AVC remedies this limitation by using variable block size motion estimation (VBSME).  ... 
doi:10.12720/joace.3.1.51-55 fatcat:3ttm53krpbgotffsc6hqbrkwiq
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