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A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing

M. MIYAHARA, A. MATSUZAWA
2008 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
This paper proposes a performance model for design of pipelined analog-to-digital converters (ADCs).  ...  The conversion frequency of ADC is improved by choosing the optimum overdrive voltage of the transistor, an important consideration at smaller design rules.  ...  Acknowledgments This work is supported by the Semiconductor Technology Academic Research Center (STARC), VLSI Design and Education Center (VDEC) and the University of Tokyo in collaboration with Cadence  ... 
doi:10.1093/ietfec/e91-a.2.469 fatcat:o2ry42icdvaglefeacc5r4ur7a

A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter

Tomohiko Ito, Takeshi Ueno, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura
2005 IEICE Electronics Express  
The optimum bit/stage configuration is an important issue in the design of a low-power pipeline analog-to-digital converter (ADC).  ...  A test chip was fabricated for confirmation, and a power dissipation of 105 mW was achieved.  ...  Acknowledgement This work was supported by the National Institute of Information and Communication Technology (NICT).  ... 
doi:10.1587/elex.2.429 fatcat:csv62ax52ba3tlalpcvqkwez64

Systematic design for power minimization of pipelined analog-to-digital converters

R. Lotfi, M. Teherzadeh-Sani, M.Y. Azizi, O. Shoaei
2003 ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)  
In this paper a general method to design a pipelined ADC with minimum power consumption is presented.  ...  To determine the bias current values of operational amplifiers an optimal choice for settling and slewing time parameters is proposed.  ...  of our design), and V eff (the minimum value for the overdrive voltage of the input devices, equal to 150mV here) are initially determined for the optimization CAD tool.  ... 
doi:10.1109/iccad.2003.159714 fatcat:ws53o7jbtraknehjajfop56uqa

Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

Jie Yuan
2009 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Results from the EBM match those from real circuit models well, except for the noise of SI MDACs with feedback, in which case, the design margin should be added to the target performance.  ...  For low-/medium-resolution ( 12 bit) applications, a pipeline ADC with a simple SI MDAC is the most efficient. Nonetheless, single-ended SI ADCs are susceptible to source noise.  ...  PIPELINE ADC The structure of a pipeline ADC is shown in Fig. 2 . Each pipeline stage includes a flash ADC and an MDAC.  ... 
doi:10.1109/tcsi.2008.2003379 fatcat:3v2oeybwy5gk7d752lt2zj5znq

An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit

Shan Jiang, Manh Anh Do, Kiat Seng Yeo, Wei Meng Lim
2008 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
For speed consideration, the slewing time should be minimized, which requires a high opamp slew rate. The opamp with a high slew rate settles to the final value in the linear settling phase.  ...  The INL curve has three jumps and is similar to the INL of a pipelined ADC with 2-bit first stage.  ... 
doi:10.1109/tcsi.2008.916613 fatcat:tg47ykdiivaubcwmmcdyqospnm

A low-power design methodology for high-resolution pipelined analog-to-digital converters

Reza Lotfi, Mohammad Taherzadeh-Sani, M. Yaser Azizi, Omid Shoaei
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
In this paper a general method to design a pipelined ADC with minimum power consumption is presented.  ...  To determine the bias current values of operational amplifiers, a novel optimal choice for settling and slewing time parameters is proposed applicable to both single-stage and two-stage Miller-compensated  ...  Consider a 12-bit 3.3-V 50M-Samples/sec pipeline ADC. With a full-scale voltage swing of 2V p-p,diff (i.e.  ... 
doi:10.1145/871506.871590 dblp:conf/islped/LotfiTAS03 fatcat:gibsblywezaqvp4rvwrswy3voy

A low-power design methodology for high-resolution pipelined analog-to-digital converters

Reza Lotfi, Mohammad Taherzadeh-Sani, M. Yaser Azizi, Omid Shoaei
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
In this paper a general method to design a pipelined ADC with minimum power consumption is presented.  ...  To determine the bias current values of operational amplifiers, a novel optimal choice for settling and slewing time parameters is proposed applicable to both single-stage and two-stage Miller-compensated  ...  Consider a 12-bit 3.3-V 50M-Samples/sec pipeline ADC. With a full-scale voltage swing of 2V p-p,diff (i.e.  ... 
doi:10.1145/871589.871590 fatcat:wars7gqtefexphurwdhheveih4

A full-custom ASIC design of a 8-bit, 25 MHz, Pipeline ADC using 0.35 um CMOS technology [article]

Moslem Rashidi, Mikael Hogrud, Donatas Siaudinis, Affaq Qamar, Imran Khan
2012 arXiv   pre-print
The purpose of this project was to design and implement a pipeline Analog-to-Digital Converter using 0.35um CMOS technology.  ...  A differential switched capacitor circuit consisting of a cascade gm-C op-amp with 200MHz ft is used for sampling and amplification in each stage [12].  ...  This in conjunction with the requirements on Bandwidth and Slew rate we got from the Simulink model and the desired signal swing gave us the necessary information to distribute the overdrive voltages and  ... 
arXiv:1011.4157v2 fatcat:nbzn23risncchixq3gzn56zxpi

Ring amplifiers for switched-capacitor circuits

Benjamin Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon
2012 2012 IEEE International Solid-State Circuits Conference  
swing), and performance that scales with process technology.  ...  The second fabricated IC presented is a high-resolution pipelined ADC which employs the technique of Split-CLS to perform efficient, accurate amplification aided by ring amplifiers.  ...  ACKNOWLEDGMENT The authors would like to thank Asahi Kasei Microdevices for supporting this research.  ... 
doi:10.1109/isscc.2012.6177090 dblp:conf/isscc/HershbergWSTHM12 fatcat:6q4xs3znfrbadghizkgnmzxxda

Ring Amplifiers for Switched Capacitor Circuits

Benjamin Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon
2012 IEEE Journal of Solid-State Circuits  
swing), and performance that scales with process technology.  ...  The second fabricated IC presented is a high-resolution pipelined ADC which employs the technique of Split-CLS to perform efficient, accurate amplification aided by ring amplifiers.  ...  ACKNOWLEDGMENT The authors would like to thank Asahi Kasei Microdevices for supporting this research.  ... 
doi:10.1109/jssc.2012.2217865 fatcat:mpqw4jmsufblhohbnwnu5mcu2i

Design Approach for Ring Amplifiers

Joschua Conrad, Patrick Vogelmann, Mohamed Aly Mokhtar, Maurits Ortmanns
2020 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
The proposed optimization process is successfully performed using 180 nm and 40 nm technology nodes (second node with two supply voltages) and the three designs are analyzed and compared.  ...  The optimization process is derived from a simple ring-amplifier model and a stability criterion.  ...  Stability Criterion and Considerations The initial ramping happens with the maximum possible overdrive for the output stage.  ... 
doi:10.1109/tcsi.2020.2986553 fatcat:sgxpbpmngreuni7235imzdoztq

Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture

H.-H. OU, S.-J. CHANG, B.-D. LIU
2008 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
This paper proposes useful circuit structures for achieving a low-voltage/low-power pipelined ADC based on switched-opamp architecture.  ...  Second, opamp-sharing is merged into switched-opamp structure with a proposed dual-output opamp configuration. A 0.8-V, 9-bit, 10-Msample/s pipelined ADC is designed to verify the proposed circuit.  ...  Acknowledgments This work was supported by the Ministry of Economic Affairs under Grant 95-EC-17-A-01-S1-031.  ... 
doi:10.1093/ietfec/e91-a.2.461 fatcat:cwnezkeiizgorgmtcubws272l4

Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters

T. Sundstrom, B. Murmann, C. Svensson
2009 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
In this paper, we present an attempt to estimate a lower bound for the power of ADCs, based on first principles and using pipeline and flash architectures as examples.  ...  Two published ADCs are used for a more detailed comparison between the minimum bound and today's designs.  ...  For the 90-nm data, we note that, with typical gate-overdrive voltages used in analog designs of 100-300 mV, we have mV, following neither the strong-inversion formula (which predicts mV) nor the weak-inversion  ... 
doi:10.1109/tcsi.2008.2002548 fatcat:ymgtu4xosnevzb63lxsjcosxz4

Technology trend of ADCs

Akira Matsuzawa
2008 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)  
Matsuzawa, "A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing", IEICE TRANS. ELECTRON, vol. E91-A, No.2, pp.469-475, Feb. 2008. .  ...  Mori, and S. Tsukamoto "A 0.8V 10b 80MS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing," ISSCC, Dig. Tech. paper, pp. 452-453, 2007. 24 Matsuzawa & Okada Lab.  ... 
doi:10.1109/vdat.2008.4542441 fatcat:eadhkpt44vgktg7uy7q67icbxa

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

Yun Chiu, P.R. Gray, B. Nikolic
2004 IEEE Journal of Solid-State Circuits  
The ADC occupies an active area of 10 mm 2 and dissipates 98 mW.  ...  The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit  ...  ACKNOWLEDGMENT The authors would like to thank ST Microelectronics for providing the chip fabrication, and the Data Conversion Systems Group of National Semiconductor Corporation for help with testing.  ... 
doi:10.1109/jssc.2004.836232 fatcat:wmpuk7crqzht7intpvx6rggbf4
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