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A performance comparison of hierarchical ring- and mesh-connected multiprocessor networks

G. Ravindran, M. Stumm
Proceedings Third International Symposium on High-Performance Computer Architecture  
This paper compares the performance of hierarchical ring-and mesh-connected wormhole routed shared memory multiprocessor networks in a simulation study.  ...  Hierarchical rings are interesting alternatives to meshes since i) they can be clocked at faster rates, ii) they can have wider data paths and hence shorter message sizes, iii) they allow addition and  ...  In this paper, we analyse and compare the performance of hierarchical ring and mesh connected multiprocessor networks, using detailed it-level simulations.  ... 
doi:10.1109/hpca.1997.569606 dblp:conf/hpca/RavindranS97 fatcat:7pzaj7oajjg2vjywpmhrhmrlsy

A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing

S. Bourduas, Z. Zilic
2007 First International Symposium on Networks-on-Chip (NOCS'07)  
This paper presents a hybrid architecture that partitions a large 2D-mesh into several smaller sub-meshes which are globally connected using a hierarchical ring interconnect.  ...  By partitioning a two-dimensional mesh into several sub-meshes and connecting them using a global interconnect, we can reduce the average number of hops for global traffic.  ...  In [13] , a reconfigurable system which uses a hierarchical mesh interconnection network consisting of nearest neighbor connectivity at the lowest level of the hierarchy and horizontal and vertical buses  ... 
doi:10.1109/nocs.2007.3 dblp:conf/nocs/BourduasZ07 fatcat:4ok27pagknhhtdio3p2ynhpxrm

On-chip implementation of multiprocessor networks and switch fabrics

Terry Tao Ye, Giovanni De Micheli
2008 International Journal of Embedded Systems  
On-chip implementation of multiprocessor systems needs to planarise the interconnect networks onto the silicon floorplan.  ...  Compared with traditional ASIC/SoC architectures, Multiprocessor Systems on Chips (MPSoC) node processors are homogeneous, and MPSoC network topologies are regular.  ...  CCC networks have a hierarchical structure: the three nodes at each corner of the cube form a local ring.  ... 
doi:10.1504/ijes.2008.022392 fatcat:4qmhz2u7mvcmnphgevwp63lmju

A comparative study of bidirectional ring and crossbar interconnection networks

Hitoshi Oi, N. Ranganathan
2002 Computers & electrical engineering  
For distributed shared memory multiprocessors, the choice and the design of interconnection networks have a significant impact on their performance.  ...  Our study shows that for a configuration of 32 nodes, the bidirectional ring outperforms the crossbar by 37% on the average of four parallel applications.  ...  Related Work Ravindran and Stumm compared the performance of multiprocessors using hierarchical ring and mesh networks [4] . The miss latency was used for performance comparison.  ... 
doi:10.1016/s0045-7906(00)00044-6 fatcat:7xtrp4riefcllpl35ku4obyq5m

Design and implementation of the NUMAchine multiprocessor

A. Grbic, M. Stumm, Z. Vranesic, Z. Zilic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless, N. Manjikian, S. Srbljic
1998 Proceedings of the 35th annual conference on Design automation conference - DAC '98  
This paper describes the design and implementation of the NUMAchine multiprocessor.  ...  As the market for CC-NUMA multiprocessors expands, this research project provides a timely architectural design and cost-effective prototype.  ...  The Stanford DASH [5] multiprocessor is a mesh-based system that uses separate request and response communication networks.  ... 
doi:10.1145/277044.277057 dblp:conf/dac/GrbicBCGGLLMSSVZ98 fatcat:zku2cnlt55cp5nshogbyxiqsly

Hierarchical ring network configuration and performance modeling

V.C. Hamacher, Hong Jiang
2001 IEEE transactions on computers  
AbstractÐApproximate analytical queuing network models for expected message packet delay in 2-level and 3-level hierarchical ring interconnection networks (INs) are developed.  ...  A major class of traffic carried by these INs consists of cache line transfers between processor caches and remote memory modules in shared-memory multiprocessors.  ...  The research of Hong Jiang was supported in part by a Nebraska Research Initiative (NRI) Research Grant.  ... 
doi:10.1109/12.902749 fatcat:t3azrgfatrb3pdsrb6c4l6t6ee

System-level analysis of mesh-based hybrid optical-electronic network-on-chip

Yaoyao Ye, Xiaowen Wu, Jiang Xu, Mahdi Nikdast, Zhehui Wang, Xuan Wang, Zhe Wang
2013 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)  
Network-on-chip (NoC) can improve the performance, power efficiency, and scalability of multiprocessor systemon-chip (MPSoC).  ...  We propose a low-cost mesh-based hybrid opticalelectronic NoC, HOME, with non-blocking 5x5, 4x4 and 3x3 optical switching fabrics.  ...  Kirman et al. proposed a hierarchical optoelectrical system, where an optical ring is used to connect electronic clusters [6] .  ... 
doi:10.1109/iscas.2013.6571846 dblp:conf/iscas/YeWXNWWW13 fatcat:rx4d72c775bc3iqirn7ip2mseu

Physical planning for the architectural exploration of large-scale chip multiprocessors

Javier de San Pedro, Nikita Nikitin, Jordi Cortadella, Jordi Petit
2013 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)  
This paper presents an integrated flow for architectural exploration and physical planning of large-scale hierarchical tiled CMPs.  ...  Routing is performed on top of memories and components that underutilize the available metal layers for interconnectivity.  ...  ACKNOWLEDGMENTS This research has been funded by a gift from Intel Corp., project CICYT TIN2007-66523, and FPI grant BES-2008-004612.  ... 
doi:10.1109/nocs.2013.6558399 dblp:conf/nocs/PedroNCP13 fatcat:fkavtl2kanezbdqh5gb3yknki4

A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate

Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu
2016 Parallel Computing  
Hierarchical ring networks, which hierarchically connect multiple levels of rings, have been proposed in the past to improve the scalability of ring interconnects, but past hierarchical ring designs sacrifice  ...  To this end, we revisit the concept of a hierarchical-ring network-on-chip.  ...  This article is an extended and significantly revised version of a paper that appeared at SBAC-PAD 2014 [3] .  ... 
doi:10.1016/j.parco.2016.01.009 fatcat:x5ia7fpsl5auhjs6h24qxbzg4y

Architectural approach to the role of optics in monoprocessor and multiprocessor machines

Jacques Henri Collet, Daniel Litaize, Jan Van Campenhout, Chris Jesshope, Marc Desmulliez, Hugo Thienpont, James Goodman, Ahmed Louri
2000 Applied Optics  
The bottlenecks resulting from and the benefits of implementing OI's are discussed with respect to symmetric multiprocessors, rings, and distributed shared-memory supercomputers.  ...  Therefore the higher the connectivity ͑possibly with optics͒, the shorter the path to another node, but the more expensive the network and the more complex the structure of electronic nodes.  ...  Lambkin, Dominique Lavernier, Henk Neefs, Rami Melhem, Matthias Pez, Roger Vounckx, and Zvonko Vranesic, of the WOCCS for numerous fruitful and informal discussions.  ... 
doi:10.1364/ao.39.000671 pmid:18337941 fatcat:mowm54a6b5bidk3v5epnutx2a4

Design and Evaluation of Hierarchical Rings with Deflection Routing

Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu
2014 2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing  
Hierarchical ring networks, which hierarchically connect multiple levels of rings, have been proposed in the past to improve the scalability of ring interconnects, but past hierarchical ring designs sacrifice  ...  than multiple versions of both a previous hierarchical ring design and a traditional single ring design.  ...  ACKNOWLEDGMENTS We thank the reviewers and SAFARI members for their feedback. We acknowledge the support of AMD, IBM, Intel, and Qualcomm.  ... 
doi:10.1109/sbac-pad.2014.31 dblp:conf/sbac-pad/AusavarungnirunFYCNDLM14 fatcat:oniwh2qpi5bg7owgscmw4jivu4

Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing [article]

Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu
2016 arXiv   pre-print
Hierarchical ring networks, which hierarchically connect multiple levels of rings, have been proposed in the past to improve the scalability of ring interconnects, but past hierarchical ring designs sacrifice  ...  HiRD attains equal or better performance at better energy efficiency than multiple versions of both a previous hierarchical ring design and a traditional single ring design.  ...  This article is a significantly extended and revised version of our previous work that appeared at SBAC-PAD 2014 [5] .  ... 
arXiv:1602.06005v1 fatcat:xnudls56ozdhbfeo6cpgecqulq

Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors

Carmen Martínez, Enrique Vallejo, Ramón Beivide, Cruz Izu, Miquel Moretó
2006 International journal of parallel programming  
This paper introduces a new two-dimensional node's labeling of the networks explored which simplifies their analysis and exploitation.  ...  Other implementation issues such as network folding and scalability by using hierarchical networks are also explored in this work.  ...  The simplest bi-dimensional topology is a 2D Mesh, whose longest path connects any pair of nodes located in opposite corners. Thus, the diameter of a N-node 2D Mesh is 2( √ N − 1).  ... 
doi:10.1007/s10766-006-0014-1 fatcat:wmwcwm6qefdbrhqrsf63jioleu

Chip Multiprocessor Traffic Models Providing Consistent Multicast and Spatial Distributions

Dietmar Tutsch, Daniel Lüdtke
2008 Simulation (San Diego, Calif.)  
These cores are connected on-chip by a bus or, if many cores are involved, by an appropriate network.  ...  Chip multiprocessors (CMPs) have become the center of attention in recent years. They consist of multiple processor cores on a single chip.  ...  They investigated the performance of particular architectures of buses and rings dependent on spatial localities. Shared and hierarchical buses are used.  ... 
doi:10.1177/0037549708091638 fatcat:opux7kwufbcwra6wgd2qh6ewcm

Applying 4-regular grid structures in large-scale access networks

Jens Myrup Pedersen, Ahmed Patel, Thomas Phillip Knudsen, Ole Brun Madsen
2006 Computer Communications  
ring and tree structures.  ...  4-Regular grid structures have been used in multiprocessor systems for decades due to a number of nice properties with regard to routing, protection, and restoration, together with a straightforward planar  ...  Acknowledgements We would like to thank University College Dublin for hosting Jens Myrup Pedersen and Thomas Phillip Knudsen as visiting researchers during the work of this paper, as well as Nikita Schmidt  ... 
doi:10.1016/j.comcom.2005.07.020 fatcat:stjc6yg2sferda6yyinisgtwzq
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