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A parallel precorrected FFT based capacitance extraction program for signal integrity analysis

N. R. Aluru, V. B. Nadkarni, J. White
1996 Proceedings of the 33rd annual conference on Design automation conference - DAC '96  
In this paper, we examine parallelizing the precorrected FFT algorithm for 3-D capacitance extraction and present several algorithms for balancing workload and reducing communication time.  ...  In order to optimize interconnect to avoid signal integrity problems, very fast and accurate 3-D capacitance extraction is essential.  ...  Nabors for providing the Fastcap and precorrected FFT software on which these experiments were based.  ... 
doi:10.1145/240518.240587 dblp:conf/dac/AluruNW96 fatcat:xmbl2oax6zg4vkv2hoi2faxcme

A parallel precorrected FFT based capacitance extraction program for signal integrity analysis

N.R. Aluru, V.B. Nadkarni, J. White
33rd Design Automation Conference Proceedings, 1996  
In this paper, we examine parallelizing the precorrected FFT algorithm for 3-D capacitance extraction and present several algorithms for balancing workload and reducing communication time.  ...  In order to optimize interconnect to avoid signal integrity problems, very fast and accurate 3-D capacitance extraction is essential.  ...  Nabors for providing the Fastcap and precorrected FFT software on which these experiments were based.  ... 
doi:10.1109/dac.1996.545602 fatcat:nsrsceqgkfervl6usrkcail3qq

A Parallel Implementation of a Fast Multipole-Based 3-D Capacitance Extraction Program on Distributed Memory Multicomputers

Yanhong Yuan, Prith Banerjee
2001 Journal of Parallel and Distributed Computing  
This paper examines the parallelization of the well known fast multipole based 3-D capacitance extraction program , which employs new preconditioning and adaptive techniques.  ...  Very fast and accurate 3-D capacitance extraction is essential for interconnect optimization in ultra deep submicro designs (UDSM).  ...  White and his group at MIT for providing the FASTCAP program, the associated examples and documents, on which these experiments were based.  ... 
doi:10.1006/jpdc.2001.1725 fatcat:y66asammfzbp7habtey7h4dr6i

ParAFEMCap: A Parallel Adaptive Finite-Element Method for 3-D VLSI Interconnect Capacitance Extraction

Genlong Chen, Hengliang Zhu, Tao Cui, Zhiming Chen, Xuan Zeng, Wei Cai
2012 IEEE transactions on microwave theory and techniques  
In this paper, a parallel adaptive finite-element method (AFEM) for capacitance extraction of large-scale interconnects (ParAFEMCap) is developed to provide extremely high parallel scalability and numerical  ...  Moreover, ParAFEMCap is shown to have the same linear computation complexity as those integral-equation methods, which make it very promising for capacitance extraction of large-scale interconnect problems  ...  PARAFEMCAP: PARALLEL IMPLEMENTATION OF AFEM FOR INTERCONNECT CAPACITANCE EXTRACTION The parallel adaptive FEM for interconnect capacitance extraction (ParAFEMCap) is developed in this section based on  ... 
doi:10.1109/tmtt.2011.2176137 fatcat:z7ieyvbw25hjlhjh43hxjneryq

Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method

Wenjian Yu, Mengsheng Zhang, Zeyi Wang
2006 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
To take the floating dummies into account, an efficient method for three-dimensional (3-D) capacitance extraction based on boundary element method is proposed.  ...  Index Terms-Boundary-element method (BEM), design for manufacturability, dummy fill, interconnect capacitance extraction.  ...  Many fast algorithms based on BEM have been proposed, including the fast multipole approach [6] , hierarchical approach [7] , the precorrected fast Fourier transform (FFT) algorithm [8] , and the quasi-multiple  ... 
doi:10.1109/tcad.2005.853690 fatcat:kqzarbgc5bc4fnjgwzb5yxhk2a

INDUCTWISE: inductance-wise interconnect simulator and extractor

Tsung-Hao Chen, C. Luk, Charlie Chung-Ping Chen
2003 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We provide a theoretical analysis as well as a provable stable algorithm for it. Second, a robust window-selection algorithm is presented for general geometry.  ...  Third, integrated with the nodal analysis formulation, INDUCTWISE achieves exceptional performance without frequency-dependent complex operations and directly gives time-domain responses.  ...  Garg for his help and comment.  ... 
doi:10.1109/tcad.2003.814260 fatcat:5qoapzsinrbv7jp7uc7en3kzli

Efficient formulation and model-order reduction for the transient simulation of three-dimensional VLSI interconnect

M. Chou, J.K. White
1997 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper we describe a multipole-accelerated, mixed surfacevolume formulation, and a preconditioned model-order reduction algorithm for distributed RC, or electroquasistatic, simulation of 3-D integrated  ...  Results are presented to demonstrate that the computational cost for extracting a complete reduced-order model is order N N N, where N N N is the number of surface unknowns.  ...  Korsmeyer for making his FASTLAP program available. The multipole-accelerated algorithms in the code were mostly based on FASTLAP. They would also like to acknowledge D.  ... 
doi:10.1109/43.664228 fatcat:k4yhf6fjrjgarozo72wre7aule

Emerging simulation approaches for micromachined devices

T. Mukherjee, G.K. Fedder, D. Ramaswamy, J. White
2000 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Lastly, we describe the recently developed circuit-based approach for simulating micromachined devices, and describe the design hierarchy and the use of a catalog of parts.  ...  In this survey paper, we describe and contrast three different approaches for extending circuit simulation to include micromachined devices.  ...  The program uses the precorrected-FFT accelerated integral equation solver [29] with planar triangular panels to compute the electrostatic forces.  ... 
doi:10.1109/43.898833 fatcat:7caab7yioven3ahbytjjvuefqu

Hybrid integration of light-emitters and detectors with SOI-based micro-opto-electro-mechanical systems (MOEMS)

Joel A. Kubby, Jim Calamita, Jen-Tsorng Chang, Jingkuang Chen, Peter Gulvin, C.-C. Lin, Robert Lofthus, Bill Nowak, Yi Su, Alex Tran, David Burns, Janusz Bryzek (+22 others)
2001 Silicon-based and Hybrid Optoelectronics III  
A three-layer polysilicon process consisting of two structural layers is integrated on top of the silicon device layer.  ...  A key goal is to overcome the shortcomings of the polysilicon layer used for fabricating optical components in a conventional surface micromachining process.  ...  ACKNOWLEDGEMENTS Work performed under Cooperative Agreement #70NANB8H4014, National Institute for Standards and Technology Advanced Technology Program, ATP Project Managers Gerald V.  ... 
doi:10.1117/12.426941 fatcat:ifdxu347abf5lnzk7qvtczdivm

A parallel implementation of a fast multipole based 3-D capacitance extraction program on distributed memory multicomputers

Yanhong Yuan, P. Banerjee
Proceedings 14th International Parallel and Distributed Processing Symposium. IPDPS 2000  
This paper examines the parallelization of the well known fast multipole based 3-D capacitance extraction program , which employs new preconditioning and adaptive techniques.  ...  Very fast and accurate 3-D capacitance extraction is essential for interconnect optimization in ultra deep submicro designs (UDSM).  ...  White and his group at MIT for providing the FASTCAP program, the associated examples and documents, on which these experiments were based.  ... 
doi:10.1109/ipdps.2000.846002 dblp:conf/ipps/YuanB00 fatcat:fuyjckxjarfn5pcrqg6lqn2a5q

Implementation of algorithms to determine the capacitance sensitivity of interconnect parasitics in the Magic VLSI layout tool [article]

Nick Kuan-Hsiang Huang
2009
In addition, a simple technique to extract from layout the sensitivity of interconnect parasitic capacitance to linewidth process variation is proposed based on the new capacitance models and implemented  ...  A new set of capacitance models is implemented in the Magic VLSI layout tool to improve the capacitance accuracy based on 2.5D capacitance models.  ...  In 1991, a 3-D capacitance extraction program based on the multipole expansions was published: FastCap [57] .  ... 
doi:10.14288/1.0067690 fatcat:sjismhemkfdv7ljw7jq43ichk4

Comprehensive frequency-dependent substrate noise analysis using boundary element methods

Hongmei Li, J. Carballido, H.H. Yu, V.I. Okhmatovski, E. Rosenbaum, A.C. Cangellaris
IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.  
This paper presents a highly accurate technique, based on a precorrected-FFT approach, that speeds up this calculation.  ...  In this paper we describe one popular formulation used to analyze biomolecule electrostatics, present an integral formulation of the problem, and apply the precorrected-FFT method to accelerate the solution  ...  capacitance.  ... 
doi:10.1109/iccad.2002.1167506 fatcat:xsqqw7lg2zcbnk5y7uyqfhebnq

Contact mechanics perspective of tribology [article]

(:Unkn) Unknown, Technische Universität Berlin, Irina G. Goryacheva, Marco Paggi, Valentin L. Popov
2021
A time to throw stones and a time to gather stones (Ecclesiastes 3:5) It is a time to gather stones...  ...  on the contributions of the International Workshop "Contact Mechanics and Friction: Foundations and Applications", TU Berlin, 14.-17, October 2019, but is also open for other contributions.  ...  ACKNOWLEDGMENTS The authors thank the DFG (German Research Foundation) for supporting this project in the context of the research program the SFB Tailored Forming in the subproject C3.  ... 
doi:10.14279/depositonce-12169 fatcat:awicgyyejfeblhtjcmz26z4nbq