A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2010; you can also visit the original URL.
The file type is application/pdf
.
Filters
A PRAM and NAND flash hybrid architecture for high-performance embedded storage subsystems
2008
Proceedings of the 7th ACM international conference on Embedded software - EMSOFT '08
To do this, we first propose a new hybrid storage architecture which consists of PRAM and NAND flash. ...
In this paper, we focus on developing a high-performance NAND flash-based storage system by maximally exploiting the advanced feature of PRAM, in terms of performance and wearing out. ...
So, instead of providing complete replacement scheme of NAND flash, we propose a hybrid storage architecture of PRAM and NAND flash memory, as shown in Figure 1 . ...
doi:10.1145/1450058.1450064
dblp:conf/emsoft/KimLCB08
fatcat:tkh57wwfprexlm5owj5tu5cpmm
What is the future of disk drives, death or rebirth?
2011
ACM Computing Surveys
The architectural design of disk drives has reached a turning point which should allow their performance to advance further, while still maintaining high reliability and energy efficiency. ...
Fourthly, it introduces some new storage media types and the impacts they have on the architecture of the traditional disk drives. ...
Jose Martinez and the editors of ACM Computing Surveys for giving me the opportunity to clarify my thoughts. This work was funded in part by a startup research fund from Jinan University. ...
doi:10.1145/1922649.1922660
fatcat:zz3kcy54gfh4zj2oauq455ozxq
A Survey of Hybrid Main Memory Architectures
2019
Sakarya University Journal of Science
In this research, we investigate hybrid main memory systems for a more efficient main memory architecture. ...
Another study to address this increasing demand is the development of hybrid main memory architectures. Hybrid Main Memory is one of the most recent studies on RAM. ...
Figure 11 : ECC for hybrid DRAM/PRAM [33] For achieving high performance of DRAM + PRAM hybrid architecture, an architecture that can be accessed in parallel with memories (shown in Fig. 12 ) has been ...
doi:10.16984/saufenbilder.334645
fatcat:r36y2uh5azenxg6pj2n5c74a7i
Report on workshop on operating systems support for next generation large scale NVRAM (NVRAMOS 2009)
2009
SIGMOD record
The simulator not only explored the internal architecture of SSD, but also considered both the H/W (Channel/Way, DRAM cache management, Hybrid Flash memory arrays such as MLC+SLC combination, etc.) and ...
MOTIVATIONS NAND Flash memory solid state disk (hereafter SSD) technology is advancing rapidly in capacity and speed. ...
doi:10.1145/1815918.1815931
fatcat:fqsnm3nldvbmfncvwguvhxakfe
NVM Storage in IoT Devices: Opportunities and Challenges
2021
Computer systems science and engineering
This paper classifies the different storage architectures based on NVM and compares the system goals, architectures, features, and limitations to explore new research opportunities. ...
However, with the explosion of data and higher real-time requirements, the traditional Internet of Things (IoT) storage architecture cannot meet the requirements of low latency and large capacity. ...
Guo Yeting for his assistance in this paper.
Conflicts of Interest: The authors declare that they have no conflicts of interest to report regarding the present study. ...
doi:10.32604/csse.2021.017224
fatcat:uu4bprtlnfglrlpafsnjjlvqfq
While non-volatile memory (NVRAM) devices have the potential to alleviate the trade-off between performance, scalability, and energy in storage and memory subsystems, a block interface and storage subsystems ...
designed for slow I/O devices make it difficult to efficiently exploit NVRAMs in a portable and extensible way. ...
This research was supported in part by the National Science Foundation under award IIP-1266400 and industrial members of the Center for Research in Storage Systems(CRSS). ...
doi:10.1145/2611354.2611364
dblp:conf/systor/KangPMM14
fatcat:aeuefdqrgrfgdb2fwliee2u2li
Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies
2020
IEEE Access
In addition to memory modules, DIMMs are a common form of connectors for high speed storage modules to CPU cores.
3) NON-VOLATILE NAND (NV-NAND) In general, memory (i.e., DRAM) is expensive, provides ...
PRAM is a memory storage cell type that can be incorporated in the DRAM, but also directly inside the accelerators and CPUs. ...
doi:10.1109/access.2020.3008250
fatcat:kv4znpypqbatfk2m3lpzvzb2nu
NVM-Shelf: Secure Hybrid Encryption with Less Flip for Non-Volatile Memory
2020
Electronics
Since the CTR mode requires additional storage for the nonce, we classify write-intensive cache blocks and apply our CTR mode to the write-intensive blocks and apply the ECB mode for the rest of the blocks ...
The Non-Volatile Memory (NVM), such as PRAM or STT-MRAM, is often adopted as the main memory in portable embedded systems. ...
On the other hand, block access only supporting global memory limits SPM integration to the sequential architecture. These include NAND flash and some PRAM based memories. ...
doi:10.3390/electronics9081304
fatcat:h724lolcxzbbrjpdlqdaob4ubu
Phase Change Memory
2010
Proceedings of the IEEE
Innovations in the device structure, memory cell selector, and strategies for achieving multibit operation and 3-D, multilayer high-density memory arrays are described. ...
The electrical and thermal properties of phase change materials are surveyed with a focus on the scalability of the materials and their impact on device design. ...
Jim McVittie for the technical support and discussions. ...
doi:10.1109/jproc.2010.2070050
fatcat:lyeb2mls2jfvjf7mmnpmszgj2a
Data center evolution
2009
Computer Networks
We define a layered model for such data centers and provide a detailed treatment of state of the art and emerging challenges in storage, networking, management and power/thermal aspects. ...
Data centers form a key part of the infrastructure upon which a variety of information technology services are built. ...
Bhuvan Urgaonkar of Pennsylvania State University for his substantial contributions to the Storage and Power/Thermal sections of this paper. ...
doi:10.1016/j.comnet.2009.10.004
fatcat:7tfgno3j45bwnlljd6f6iww6jy
Isolation in Cloud Storage
2017
Seungryoul Maeng while focusing on designing new computer architectures and NAND flash-based SSDs. ...
He worked as a journalist and translator for two years. ...
A SSD is composed of multiple NAND flash memory chips. The NAND flash memory stores data persistently using a floating gate, which is an vice and Table 1.3 summarizes the interfaces. ...
doi:10.7298/x4w95741
fatcat:epx4m3pagfb5ndxlkrpts4zazq
Traversing large graphs in realistic settings
[article]
2009
We characterize the performance of NAND flash based storage devices, including many solid state disks. ...
We also consider I/O-efficient BFS algorithms for the case when a hard disk and a solid state disk are used together. ...
And last but not the least, I would like to thank my wife Georgiana Ifrim for her unflinching love through the thick and thin. ...
doi:10.22028/d291-25941
fatcat:zt6luwhokvh7npqcwoidyd2dty
Energy-efficient Memory System Design with Spintronics
2019
Consequently, improving the energy-efficiency and performance of memory systems is an important challenge for computing system designers. ...
Spintronic memories, which offer several desirable characteristics - near-zero leakage, high density, non-volatility and high endurance - are of great interest for designing future memory systems. ...
.: STT-MRAM bit-cell
1.2.2 Domain Wall Memory (DWM)
Ferromagnetic nanowire
Fixed domain
MTJ
I shift right
I shift left
SRAM
STT-MRAM
FLASH-NOR
FLASH-NAND
DRAM
FeRAM
PCRAM
DWM ...
doi:10.25394/pgs.7479371.v2
fatcat:zu7tgm56pzabtd4sa2klmlhk6i
Dagstuhl Reports, Volume 4, Issue 11, November 2014, Complete Issue
[article]
2015
The machine provides vast amounts of persistent low latency storage via memristor technologies with performance much closer to DRAM than NAND flash. ...
Hybrid systems represent an important and powerful formalism for modeling real-world applications such as embedded systems. ...
Allowing a limited number of heap violating nodes and by strengthening the heap condition in bottom trees this construction bypasses a well-known bound for heaps. ...
doi:10.4230/dagrep.4.11
fatcat:zzps76cx7rfldla5z5dikvsqbe