Filters








23 Hits in 4.7 sec

A Programmable Video Platform and Its Application Mapping Framework Using the Target Application's SystemC Models

Daewoong Kim, Kilhyung Cha, Do-Sun Hong, Soonwoo Choi, Soo-Ik Chae
2011 EURASIP Journal on Embedded Systems  
The tightly coupled-thread (TCT) platform [6], which targets for multimedia applications including a 400 × 300 image JPEG encoder, consists of six customized RISC processors.  ...  In the platform, the RISC processors are connected with a FIFO-based point-to-point, full crossbar network with a simple hand-shake protocol for easy communication and synchronization among tightly coupled  ...  Each PIPE processor is composed of three tightly coupled processors which concurrently perform loading input data, processing them, and storing the results.  ... 
doi:10.1155/2011/373509 fatcat:rdnqcaezizcbpbuiatddj72q4e

CORNET 2.0: A Co-Simulation Middleware forRobot Networks [article]

Srikrishna Acharya, Bharadwaj Amrutur, Mukunda Bharatheesha, Yogesh Simmhan
2021 arXiv   pre-print
We present a networked co-simulation framework for multi-robot systems applications.  ...  We require a simulation framework that captures both physical interactions and communications aspects to effectively design such complex systems.  ...  CASE STUDY II: Controllability of inverted pendulum In this scenario, we control an inverted pendulum with a PID controller from a remote mobile station.  ... 
arXiv:2109.06979v1 fatcat:5wwzrhs5dzguvpxshjlgnt7fta

A Soft Dual-Processor System with a Partially Run-Time Reconfigurable Shared 128-Bit SIMD Engine

Jose Raul Garcia Ordaz, Dirk Koch
2018 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)  
In this work, we present a soft dual-processor system that, as a distinctive feature, seamlessly integrates a partially run-time reconfigurable 128-bit SIMD engine.  ...  Importantly, the SIMD engine is tightly coupled to both scalar CPUs and it is shared amongst them with the purpose of drastically improving overall area utilization.  ...  In contrast, our proposed PRR SIMD engine is very tightly coupled to the main pipelines of both system CPUs as described in Section III. III.  ... 
doi:10.1109/asap.2018.8445115 dblp:conf/asap/OrdazK18 fatcat:gckiewwtdvbe5kpodi72jenjja

Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI [article]

Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini
2020 arXiv   pre-print
We finally propose a controller architecture relying on the derived models to automatically regulate at run-time the body bias voltage.  ...  The proposed method relies on on-line performance measurements by means of Process Monitoring Blocks (PMBs) coupled with an on-chip low-power body bias generator.  ...  Once the models have been obtained, we developed a closed loop control strategy for the body bias voltage based on a simple PID controller.  ... 
arXiv:2007.13667v1 fatcat:45jx7qoieng4ffx5hqasxqrlzy

HEAL-WEAR: An Ultra-Low Power Heterogeneous System for Bio-Signal Analysis

Loris Duch, Soumya Basu, Ruben Braojos, Giovanni Ansaloni, Laura Pozzi, David Atienza
2017 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
The run-time behavior on the system is orchestrated by a light-weight hardware mechanism, which concurrently synchronizes processors for SIMD execution and regulates access to the reconfigurable accelerator  ...  Its heterogeneous structure comprises multiple processors interfaced with a shared acceleration resource, implemented as a Coarse-Grained Reconfigurable Array (CGRA).  ...  Fig. 1 . 1 HEAL-WEAR couples a multi-core processor with a CGRA unit, supporting SIMD execution in both resources.  ... 
doi:10.1109/tcsi.2017.2701499 fatcat:cdxbdrqq5raybeb743ookp77rq

Mapping irregular applications to DIVA, a PIM-based data-intensive architecture

Mary Hall, Apoorv Srivastava, William Athas, Vincent Freeh, Jaewook Shin, Joonseok Park, Peter Kogge, Jeff Koller, Pedro Diniz, Jacqueline Chame, Jeff Draper, Jeff LaCoss (+2 others)
1999 Proceedings of the 1999 ACM/IEEE conference on Supercomputing (CDROM) - Supercomputing '99  
The Data-IntensiVe Architecture (DIVA) system combines PIM memories with one or more external host processors and a PIM-to-PIM interconnect.  ...  Processing-in-memory (PIM) chips that integrate processor logic into memory devices offer a new opportunity for bridging the growing gap between processor and memory speeds, especially for applications  ...  A more recent chip is the Mitsubishi M32 R/D, where more than 2 MB of memory is tightly tied into the on-chip CPU's cache[Shimizu96].  ... 
doi:10.1145/331532.331589 dblp:conf/sc/HallKKDCDLGBSAFSP99 fatcat:6fh4yyrymbd7fkoj4tfmlr5k44

A new binary arithmetic for finite-word-length linear controllers: MEMS applications

A. K. Oudjida, A. Liacha, M. L. Berrandjia, N. Chaillet
2014 2014 9th International Design and Test Symposium (IDT)  
The radix-2 r arithmetic was applied to the hardware integration of two FWL structures: a linear time variant PID controller and a linear time invariant LQG controller with a Kalman filter.  ...  of the control performances; and easily predictable to provide a precise idea on the required logic resources before the implementation.  ...  By rethinking the architectural choices (efficiently separated and optimized decision part and datapath, both tightly tailored to the application case), it is possible to create control systems with reasonable  ... 
doi:10.1109/idt.2014.7038608 dblp:conf/idt/OudjidaLBC14 fatcat:ykr7hhrd7ndy5jbmu53hb3t7vm

HighEfficiency LowVoltage DCDC Conversion for Portable Applications [chapter]

2009 Low-Voltage/Low-Power Integrated Circuits and Systems  
of the processor.  ...  Design techniques at the power delivery system, individual control system, and circuit levels are described which help meet the stringent requirements imposed by the portable environment.  ...  One control scheme which achieves high efficiency over a wide load range is pulse-frequency modulation (PFM).  ... 
doi:10.1109/9780470545065.ch12 fatcat:jzmy5jhfb5f5pop2n5ezbnksza

Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins [article]

Jeremie S. Kim
2021 arXiv   pre-print
Third, we propose a random number generator that is based on our observation that timing failures in certain DRAM cells are randomly induced and can thus be repeatedly polled to very quickly generate true  ...  Finally, we characterize the RowHammer security vulnerability on a wide range of modern DRAM chips while violating the DRAM refresh requirement in order to directly characterize the underlying DRAM technology  ...  (a) We present data across our DRAM modules, that activation failures exhibit high spatial locality and are tightly constrained to a small number of columns (i.e., on average 3.7%/2.5%/2.2% per bank for  ... 
arXiv:2109.14520v1 fatcat:7hhrlz3tfjgx5fekdblfawxf3a

Experimental evaluation of two OpenFlow controllers

Mohamad Darianian, Carey Williamson, Israat Haque
2017 2017 IEEE 25th International Conference on Network Protocols (ICNP)  
In mission-critical networks, having a flexible and carrier-grade controller is a high priority.  ...  In a software-defined network, traffic management functionality requires a high-performance and responsive controller.  ...  the performance of OpenFlow controllers in the past couple of years.  ... 
doi:10.1109/icnp.2017.8117602 dblp:conf/icnp/DarianianWH17 fatcat:b2swd46an5f7vdv7lizig2lkiq

Hardware / Software Architectural and Technological Exploration for Energy-Efficient and Reliable Biomedical Devices

Loris Gérard Duch
2018
Regarding the kernel assignation to a datapath, it is based on the processor identifier (PID) requesting the kernel execution.  ...  An acceleration request with a lower PID is executed on lower Datapath ID (DID) inside the available RC columns.  ...  Secondly, I have proposed a Multi-Datapath CGRA design, allowing the platform to support single-instruction multiple-data (SIMD) execution modes, both at the processor and CGRA levels.  ... 
doi:10.5075/epfl-thesis-8917 fatcat:ydp5dxq2jrfilefppajsvpej4u

Low Power SoC Design [article]

Christian Piguet
2009
The design of Low Power Systems-on-Chips (SoC) in very deep submicron technologies becomes a very complex task that has to bridge very high level system description with low-level considerations due to  ...  Some very low power System-on-Chip (SoC) will be presented in three domains: wireless sensor networks, vision sensors and mobile TV.  ...  control unit based on a CoolRISC microcontroller with SRAM low-leakage memories and a power management block.  ... 
doi:10.5170/cern-2009-006.359 fatcat:3waeyo4bf5fjbbgvg7dicd3e2i

Performance Variation in Digital Systems:Workload Dependent Modeling and Mitigation [article]

(:Unkn) Unknown, National Technological University Of Athens
2021
This leads the PID controller to act partially proactive and consider RAS events that are gradually becoming a norm on the target processor 2 .  ...  Such device-level models come at the cost of elevated simulation times, while computation complexity is tightly coupled to the form of signal activity [233] .  ...  The ratio of the dice that are working correctly, to the total number of dice A.2 CDW Approximation The computational overhead for a dynamic timing simulation of a circuit design is directly coupled  ... 
doi:10.26240/heal.ntua.21941 fatcat:6i5vt2rk3jaabdxtublpupx43y

Architectural Frameworks for Automated Design and Optimization of Hardware Accelerators

Tao Chen
2018
As technology scaling slows down and only provides diminishing improvements in general-purpose processor performance, computing systems are increasingly relying on customized accelerators to meet the performance  ...  Dave's course on memory systems is one of the most exciting classes that I took, and inspired me to pursue the research on memory optimizations for accelerators.  ...  At that time, I was a young student who was nervous about the challenges ahead, and was uncertain if I could make it to the end.  ... 
doi:10.7298/x49s1p9p fatcat:ih6oqq6mz5bblcaqqdmzq645jy

Towards a Programmable Dataplane

Han Wang
2017
processors).  ...  In 2013 and 2014, Han spent two summers at Nicira/VMware working on Software Defined Networking (SDN) controller and dataplane projects.  ...  User Interface Users must be able to easily access and control the PHY. Many resources from software to hardware must be tightly coupled to allow realtime access to the PHY.  ... 
doi:10.7298/x4416v5q fatcat:qylfjuhyhzaebk3i3ydk2n23hm
« Previous Showing results 1 — 15 out of 23 results