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An Investigation into Collaborative Novel Technology Adoption in Vertical Disintegration

Masanori YASUMOTO, Jing Ming SHIU
2007 Annals of Business Administrative Science  
Nevertheless, the adoption of a novel technology platform requires collaborative development processes between a technology platform vendor and a product developer.  ...  These findings show that effective system knowledge management through intefirm collaboration plays a critical role in the assimilation of novel technology platforms into products even in modularized interfirm  ...  Acknowledgement The study was financially supported by the Grant-in-Aid for Scientific Research B (2005Research B ( -2006Research B ( , 2007 and C (2006-), Ministry of Education, Culture, Science  ... 
doi:10.7880/abas.6.35 fatcat:hyznokjywvhfxbtlh26yabvl7a

Design experience of a chip multiprocessor merlot and expectation to functional verification

Satoshi Matsushita
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture.  ...  In this paper, we also discuss the methodology to improve functional verification coverage, and expect the solution in formal approaches.  ...  If we have a tool to generate good vectors, functional verification problems are improved even with vector based solutions; (1-i) to (1-iii) .  ... 
doi:10.1145/581199.581223 fatcat:x36o4c62hbh7vaozjrpgrwzvte

Design experience of a chip multiprocessor merlot and expectation to functional verification

Satoshi Matsushita
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture.  ...  In this paper, we also discuss the methodology to improve functional verification coverage, and expect the solution in formal approaches.  ...  If we have a tool to generate good vectors, functional verification problems are improved even with vector based solutions; (1-i) to (1-iii) .  ... 
doi:10.1145/581220.581223 fatcat:ylogpwxrprhafgn6jc2acch3vy

Intelligent Interleaving of Scenarios: A Novel Approach to System Level Test Generation

Shady Copty, Itai Jaeger, Yoav Katz, Michael Vinov
2007 Proceedings - Design Automation Conference  
We also describe a tool that implements this method and show how it was used in IBM for system verification of the Xbox 360 chip and Power Management in the Cell processor, as well as verification of the  ...  We claim that this method shortened the system level verification cycle and allowed reuse in and across projects, which led to exposure of system-level bugs in a relatively short time.  ...  chip-level bugs in a relatively short time.  ... 
doi:10.1109/dac.2007.375290 fatcat:pan26c6mgrh5tayjim3rih5je4

Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping

Chun-ming Huang, Kuen-jong Lee, Chih-chyau Yang, Wen-hsiang Hu, Shi-shen Wang, Jeng-bin Chen, Chi-shi Chen, Lan-da Van, Chien-ming Wu, Wei-chang Tsai, Jing-yang Jou
2006 2006 IEEE International SOC Conference  
In this paper, we propose a novel SoC design methodology referred to as Multi-Project System-on-a-Chip (MP-SoC), which can integrate multiple heterogeneous SoC design projects into a single chip such that  ...  A test chip named MP-SoC-I that includes 8 SoC projects from 4 universities was selected as a demonstration example for verifying the MP-SoC design concept.  ...  System Architecture Design Flow: To offer the verifying system-level performance and features, we create a system architecture design flow to further improve verification time benefits for the following  ... 
doi:10.1109/socc.2006.283867 dblp:conf/socc/HuangLYHWCCVWTJ06 fatcat:onq3gjq4nbcznmt3fmug426nrm

Heterogeneous Systems on Chip and Systems in Package

I. O'Connor, B. Courtois, K. Chakrabarty, N. Delorme, M. Hampton, J. Hartung
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
Finally, specific flows for signal abstraction heterogeneity in RF SiP and for functional co-verification are discussed.  ...  This paper discusses several forms of heterogeneity in systems on chip and systems in package.  ...  Most of the time however, these are only used for auxiliary verifications, and the system designer relies on analytical models which allow for joint simulation using system-level (e.g.  ... 
doi:10.1109/date.2007.364683 dblp:conf/date/OConnorCCDHH07 fatcat:5m2bmusl3rfahe77sj267xrzme

Physical Design Automation for 3D Chip Stacks

Johann Knechtel, Jens Lienig
2016 Proceedings of the 2016 on International Symposium on Physical Design - ISPD '16  
The concept of 3D chip stacks has been advocated by both industry and academia for many years, and hailed as one of the most promising approaches to meet ever-increasing demands for performance, functionality  ...  However, a multitude of challenges has thus far obstructed large-scale transition from "classical" 2D chips to stacked 3D chips.  ...  A representation of the whole 3D stack, usable in such a heterogeneous design environment, is called for (see Sec. 5 for a related, novel solution).  ... 
doi:10.1145/2872334.2872335 dblp:conf/ispd/KnechtelL16 fatcat:3kigpmhpnjahbow2yptm2cjrzm

2001 technology roadmap for semiconductors

A. Allan, D. Edenfeld, W.H. Joyner, A.B. Kahng, M. Rodgers, Y. Zorian
2002 Computer  
Acknowledgments We acknowledge the efforts of the many individuals who contributed to making the 2001 edition of The International Technology Roadmap for Semiconductors a successful endeavor.  ...  capture, design for verifiability, verification reuse for heterogeneous SoCs, system-level and software verification, AMS and novel device verification, test access, self-test, intelligent noise/ delay  ...  The need for a progressively higher operational frequency associated with an increasing average chip size will continue to fuel the development of novel process, design, and packaging techniques.  ... 
doi:10.1109/2.976918 fatcat:mv3q7f3l2zfjng2i5rvipkdhsi

SoCGuard: A runtime verification solution for the functional correctness of SoCs

Rawan Abdel-Khalek, Valeria Bertacco
2010 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip  
The system-on-chip design methodology is characterized by delivering a very high level of design complexity in a short development time.  ...  While this aspect is precisely what makes SoCs appealing, it also creates a unique challenge for their verification, requiring the system to be validated as a whole, besides checking the correctness of  ...  The high level of integration of these different components makes SoCs a smaller size and a higher performance alternative to multi-chip solutions.  ... 
doi:10.1109/vlsisoc.2010.5642622 dblp:conf/vlsi/Abdel-KhalekB10 fatcat:wkeov6kmsfg3pbnstqpwe7ikna

Intelligent interleaving of scenarios

Shady Copty, Itai Jaeger, Yoav Katz, Michael Vinov
2007 Proceedings - Design Automation Conference  
We also describe a tool that implements this method and show how it was used in IBM for system verification of the Xbox 360 chip and Power Management in the Cell processor, as well as verification of the  ...  We claim that this method shortened the system level verification cycle and allowed reuse in and across projects, which led to exposure of system-level bugs in a relatively short time.  ...  chip-level bugs in a relatively short time.  ... 
doi:10.1145/1278480.1278700 dblp:conf/dac/CoptyJKV07 fatcat:fl4b6uswsbee5iz5pocalvowj4

Integrating Hardware Security into a Blockchain-Based Transactive Energy Platform [article]

Shammya Shananda Saha, Christopher Gorog, Adam Moser, Anna Scaglione, Nathan G. Johnson
2020 arXiv   pre-print
This applied research paper introduces a novel framework for integrating hardware security and blockchain functionality with grid-edge devices to establish a distributed cyber-security mechanism that verifies  ...  Expanding the idea of Two Factor Authentication and Hardware Root of Trust, this work describes the development of a Cryptographic Trust Center(TM) (CTC(TM)) chip integrated into grid-edge devices to create  ...  Signature Creation and Verification Digital Signing for Data Integrity Verification Information from a grid-edge device used for data analytic, controls, user billing transactions, and more functions requires  ... 
arXiv:2008.10705v1 fatcat:a27cnkb7xvg6xjxx7akcai7vwe

Book Titled Autonomic Networking-on-Chip: Bio-Inspired Specification, Development, and Verification: An Introduction

Phan Cong Vinh
2015 EAI Endorsed Transactions on Context-aware Systems and Applications  
A response to the critical need for a global information exchange and dialogue, it is written for engineers, scientists, practitioners, and other researchers who have a basic understanding of NoC and are  ...  Despite the growing mainstream importance and unique advantages of autonomic networking-onchip (ANoC) technology, Autonomic Networking-On-Chip: Bio-Inspired Specification, Development, and Verification  ...  The book serves as a comprehensive and essential reference on autonomic networking-on-chip and is intended as a textbook for senior undergraduateand graduate-level courses.  ... 
doi:10.4108/casa.2.3.e6 fatcat:jcfrjoy5n5cgzef2peyd3uns6q

ADAC: Automated Design of Approximate Circuits [chapter]

Milan Češka, Jiří Matyáš, Vojtech Mrazek, Lukas Sekanina, Zdenek Vasicek, Tomáš Vojnar
2018 Lecture Notes in Computer Science  
In this paper, we present ADAC-a novel framework for automated design of approximate arithmetic circuits.  ...  To make ADAC easily accessible, it is implemented as a module of the ABC tool: a state-of-the-art system for circuit synthesis and verification.  ...  The framework implements a design loop including (i) a generator of candidate solutions employing genetic search algorithms, (ii) an evaluator estimating non-functional parameters of a candidate solution  ... 
doi:10.1007/978-3-319-96145-3_35 fatcat:oy4qerweivgfhhsvzc44ieobuq

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Johann Knechtel, Ozgur Sinanoglu, Ibrahim (Abe) M. Elfadel, Jens Lienig, Cliff C. N. Sze
2017 IPSJ Transactions on System LSI Design Methodology  
Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital)  ...  We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options.  ...  Acknowledgments The authors thank Sergii Osmolovskyi (TU Dresden) for his input on interposer integration (Section 2).  ... 
doi:10.2197/ipsjtsldm.10.45 fatcat:dytlj3s7ajd4rh73iz7uxom7ou

The verification and test of complex digital ICs [Guest Editor's Introduction]

M.S. Abadir, L.-C. Wang
2004 IEEE Design & Test of Computers  
This early test program generator was architecture dependent; thus, the need for a generic solution inspired the development of a model-based test generation scheme.  ...  (IBM Research Lab, Haifa), presents Genesys-Pro, a second-generation model-based testbench generator for functional verification of uniprocessors and multicore processors.  ...  In full-chip functional verification, it's common for certain units, buried deep inside a chip, to receive less coverage than other units.  ... 
doi:10.1109/mdt.2004.1277899 fatcat:fufdt6uxuzdslkewhzbj3bt3em
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