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A State of Art Survey for OS Performance Improvement

Lailan M. Haji, Subhi R.M. Zeebaree, Karwan Jacksi, Diyar Q. Zeebaree
2018 Science Journal of University of Zakho  
This paper presents a survey of the most important and state of the art approaches and models to be used for performance measurement and evaluation.  ...  The selection of metrics which will be used for monitoring the performance depends on monitoring goals and performance requirements.  ...  And also alse dependencies may effectively be eliminate by privatization of memory writes within transactions 2017 Transaction memory model N-retry software transaction memory C++ language, computer  ... 
doi:10.25271/sjuoz.2018.6.3.516 fatcat:7ssjv7qp6re5zmyob7nysjmmmi

On transactional memory concurrency control in distributed real-time programs

Sachin Hirve, Aaron Lindsay, Binoy Ravindran, Roberto Palmieri
2013 2013 IEEE International Conference on Cluster Computing (CLUSTER)  
We consider distributed transactional memory (DTM) for concurrency control in distributed real-time programs, and present an algorithm called RT-TFA.  ...  We implement the RT-TFA on top of JChronOS, a layer extending the scheduling capabilities of ChronOS for Java programs.  ...  We consider a programming model similar to Real-Time CORBA [15] : a distributed task (or simply called task, hereafter) is programmed as a thread that may read/write local as well as remote objects.  ... 
doi:10.1109/cluster.2013.6702669 dblp:conf/cluster/HirveLRP13 fatcat:gnrrtwsrczfbxb3ys7by7o2fem

General and efficient locking without blocking

Yannis Smaragdakis, Anthony Kay, Reimer Behrends, Michal Young
2008 Proceedings of the 2008 ACM SIGPLAN workshop on Memory systems performance and correctness held in conjunction with the Thirteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '08) - MSPC '08  
Standard concurrency control mechanisms offer a trade-off: Transactional memory approaches maximize concurrency, but suffer high overheads and cost for retrying in the case of actual contention.  ...  First, we discuss an adaptive criterion for switching from a locking to a transactional implementation, and back to a locking implementation if the transactional one appears to be introducing overhead  ...  Indeed, this is a standard well-formedness criterion for multi-threaded programs and even enforced by some of the best known race detectors (e.g., Eraser [9] ).  ... 
doi:10.1145/1353522.1353524 dblp:conf/asplos/SmaragdakisKBY08 fatcat:ynoe5sutbfcrlb6nykhctfa7uq

Modeling the Run-time Behavior of Transactional Memory

Zhengyu He, Bo Hong
2010 2010 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems  
In this paper, we develop a queuing theory based analytical model to evaluate the performance of transactional memory.  ...  Based on the statistical characteristics observed on actual experiments, we model each transaction as a client requesting services from the computing system.  ...  We also thank Jean Daniel Mathieu and Xiao Yu for their contributions on the experiments.  ... 
doi:10.1109/mascots.2010.39 dblp:conf/mascots/HeH10 fatcat:j7hybpca4feulgyqsxyahsrg5e

Irrevocable transactions and their applications

Adam Welc, Bratin Saha, Ali-Reza Adl-Tabatabai
2008 Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures - SPAA '08  
Finally, we present a thorough performance evaluation of the irrevocability mechanism for the different usage models.  ...  This paper describes the design of a transactional memory system that allows irrevocable actions to be executed inside of transactions.  ...  over 4x speedup in the majority of multi-threaded runs.  ... 
doi:10.1145/1378533.1378584 dblp:conf/spaa/WelcSA08 fatcat:pxsanztiwrcvzconfweqng2sqe

The adaptive transactional memory test platform

Mark Moir, Kevin Moore, Dan Nussbaum
2008 Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures - SPAA '08  
Sun has recently announced that its forthcoming multicore processor, code-named Rock, will support a form of hardware transactional memory.  ...  In this paper, we describe our Adaptive Transactional Memory Test Platform (ATMTP), a simulator that supports this feature and provides a first-order approximation of the success and failure characteristics  ...  Concluding Remarks Sun's forthcoming multi-threaded multi-core processor, code-named Rock, will provide a form of best-effort hardware transactional memory (HTM) that promises to be a major step forward  ... 
doi:10.1145/1378533.1378595 dblp:conf/spaa/MoirMN08 fatcat:eartomgij5csjievltzt34xx6y

Kicking the tires of software transactional memory

Richard M. Yoo, Yang Ni, Adam Welc, Bratin Saha, Ali-Reza Adl-Tabatabai, Hsien-Hsin S. Lee
2008 Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures - SPAA '08  
Software Transaction Memory (STM), in particular, represents a body of important TM technologies since it provides a mechanism to run transactional programs when hardware TM support is not available, or  ...  Transactional Memory (TM) promises to simplify concurrent programming, which has been notoriously difficult but crucial in realizing the performance benefit of multi-core processors.  ...  This research was conducted under the Programming Systems Lab Research Intern Program at Intel Corporation.  ... 
doi:10.1145/1378533.1378582 dblp:conf/spaa/YooNWSAL08 fatcat:ojmrrsaaybe4xmvuq4exq2l3vi

Cache Affinity Optimization Techniques for Scaling Software Transactional Memory Systems on Multi-CMP Architectures

Kinson Chan, King Tin Lam, Cho-Li Wang
2015 2015 14th International Symposium on Parallel and Distributed Computing  
Software transactional memory (STM) enhances both ease-of-use and concurrency, and is considered one of the next-generation paradigms for parallel programming.  ...  It also features an affinity-aware thread migration technique that fine-tunes thread placements by observing inter-thread transactional conflicts.  ...  This calls for a radical change in the parallel programming model.  ... 
doi:10.1109/ispdc.2015.14 dblp:conf/ispdc/ChanLW15 fatcat:nlu7ajei7jenjmwnjhogbkpzvi

Composable scheduler activations for Haskell

K. C. SIVARAMAKRISHNAN, TIM HARRIS, SIMON MARLOW, SIMON PEYTON JONES
2016 Journal of functional programming  
In this paper, we describe a novel concurrency substrate design for the Glasgow Haskell Compiler that allows multicore schedulers for concurrent and parallel Haskell programs to be safely and modularly  ...  The approach relies on abstracting the interface to the user-implemented schedulers through scheduler activations, together with the use of Software Transactional Memory to promote safety in a multicore  ...  Conclusions and Future Work We have presented a concurrency substrate design for Haskell that lets programmers write schedulers for Haskell threads as ordinary libraries in Haskell.  ... 
doi:10.1017/s0956796816000071 fatcat:w6zdte5jybamjhyii64lq6wtl4

Hybrid Replication: State-Machine-Based and Deferred-Update Replication Schemes Combined

Tadeusz Kobus, Maciej Kokocinski, Pawel T. Wojciechowski
2013 2013 IEEE 33rd International Conference on Distributed Computing Systems  
We propose a novel algorithm for hybrid transactional replication (HTR) of highly dependable services.  ...  For expressiveness, transactions can be discarded or retried on demand.  ...  The programming model of TR matches distributed transactional memory (DTM)-an extension of transactional memory (TM) [6] [7] to distributed systems.  ... 
doi:10.1109/icdcs.2013.30 dblp:conf/icdcs/KobusKW13 fatcat:t7pr3l6yuvgorf35mhhunzzp3e

HLogo: A Parallel Haskell Variant of NetLogo

Nikolaos Bezirgiannis, I. S. W. B. Prasetya, Ilias Sakellariou
2016 Proceedings of the 6th International Conference on Simulation and Modeling Methodologies, Technologies and Applications  
This paper presents HLogo, a parallel variant of the NetLogo ABM framework, that seeks to increase the performance of ABM by utilizing Software Transactional Memory and multi-core CPUs, all the while maintaining  ...  Agent-based Modeling (ABM) has become quite popular to the simulation community for its usability and wide area of applicability.  ...  Haskell runtime employs an M:N threading model, where M lightweight threads are automatically mapped to N kernel (heavyweight) threads for multi-core parallelism.  ... 
doi:10.5220/0005983501190128 dblp:conf/simultech/BezirgiannisPS16 fatcat:opxdqfxo6nb5vg3o4fxy4kl7x4

Compiler and runtime support for efficient software transactional memory

Ali-Reza Adl-Tabatabai, Brian T. Lewis, Vijay Menon, Brian R. Murphy, Bratin Saha, Tatiana Shpeisman
2006 Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation - PLDI '06  
We measure the performance of our optimizations on a 16-way SMP running multi-threaded transactional workloads.  ...  We present a highperformance software transactional memory system (STM) integrated into a managed runtime environment.  ...  We'd also like to thank Rick Hudson, Leaf Petersen, Jim Stichnoth, Jesse Fang, and other members of the Programming Systems Lab for the many discussions on transactional memory.  ... 
doi:10.1145/1133981.1133985 dblp:conf/pldi/Adl-TabatabaiLMMSS06 fatcat:p3khq7enrneatok732mqktw3ti

Compiler and runtime support for efficient software transactional memory

Ali-Reza Adl-Tabatabai, Brian T. Lewis, Vijay Menon, Brian R. Murphy, Bratin Saha, Tatiana Shpeisman
2006 SIGPLAN notices  
We measure the performance of our optimizations on a 16-way SMP running multi-threaded transactional workloads.  ...  We present a highperformance software transactional memory system (STM) integrated into a managed runtime environment.  ...  We'd also like to thank Rick Hudson, Leaf Petersen, Jim Stichnoth, Jesse Fang, and other members of the Programming Systems Lab for the many discussions on transactional memory.  ... 
doi:10.1145/1133255.1133985 fatcat:74y2op54xrfvjgvnvuxn4ozk24

D2.3 Power models, energy models and libraries for energy-efficient concurrent data structures and algorithms [article]

Phuong Hoai Ha, Vi Ngoc-Nha Tran, Ibrahim Umar, Aras Atalar, Anders Gidenstam, Paul Renaud-Goud, Philippas Tsigas, Ivan Walulya
2018 arXiv   pre-print
This deliverable reports the results of the power models, energy models and libraries for energy-efficient concurrent data structures and algorithms as available by project month 30 of Work Package 2 (  ...  It reports i) the latest results of Task 2.2-2.4 on providing programming abstractions and libraries for developing energy-efficient data structures and algorithms and ii) the improved results of Task  ...  Movidius Myriad1), a new energy complexity model (namely, EPEM -Energy-aware Parallel External Memory) for multi-threaded algorithms, the modeling of the performance and the energy consumption of data  ... 
arXiv:1801.10556v2 fatcat:y5n53z4gz5de3lzrmvd7soa26y

McRT-STM

Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hudson, Chi Cao Minh, Benjamin Hertzberg
2006 Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '06  
We describe a software transactional memory (STM) system that is part of McRT, an experimental Multi-Core RunTime.  ...  The McRT-STM implementation uses a number of novel algorithms, and supports advanced features such as nested transactions with partial aborts, conditional signaling within a transaction, and object based  ...  Sitting on top of the core services, a set of adapters translate the threading calls in different programming models into the McRT core API.  ... 
doi:10.1145/1122971.1123001 dblp:conf/ppopp/SahaAHMH06 fatcat:3uuogbmfqbg4pjvykeqdbi7pju
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