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PUF-based Anonymous Authentication Scheme for Hardware Devices and IPs in Edge Computing Environment

Jing Long, Wei Liang, Kuan-Ching Li, Dafang Zhang, Mingdong Tang, Haibo Luo
2019 IEEE Access  
As an ideal hardware solution, field programmable gate array (FPGA) becomes a mainstream technology to design a complex system. The designed modules are named as intellectual property (IP) cores.  ...  In this paper, we consider both misappropriation of hardware devices and software IPs in edge computing and propose a PUF-based IP copyright anonymous authentication scheme.  ...  To address this issues, a PUF based anonymous IP authentication technique is proposed for both hardware FPGA and software IP designs.  ... 
doi:10.1109/access.2019.2925106 fatcat:kdn643u5pjd2hlxbl67yeuxiae

Two IP protection schemes for multi-FPGA systems

Lubos Gaspar, Viktor Fischer, Tim Guneysu, Zouha Cherif Jouini
2012 2012 International Conference on Reconfigurable Computing and FPGAs  
This paper proposes two novel protection schemes for multi-FPGA systems providing high security of IP designs licensed by IP vendors to system integrators and installed remotely in a hostile environment  ...  In the first scheme, these useful properties are achieved by storing two different configuration keys inside an FPGA, while in the second scheme, they are obtained using a hardware white-box cipher for  ...  This raised a question about the security of IP designs in SRAM-based FPGAs.  ... 
doi:10.1109/reconfig.2012.6416790 dblp:conf/reconfig/GasparFGJ12 fatcat:zcgl5ghblnhftbmm6oc5zozmcm

Dynamic Intellectual Property Protection for Reconfigurable Devices

Tim Guneysu, Bodo Moller, Christof Paar
2007 2007 International Conference on Field-Programmable Technology  
The distinct advantage of SRAM-based Field Programmable Gate Arrays (FPGA) is their flexibility for configuration changes.  ...  We propose a new protection scheme for the IP of circuits in configuration bit files that provides a significant improvement to the current unsatisfying situation.  ...  A second participant is the Intellectual Property Owner (IPO), who has created some novel logic design for a specific problem.  ... 
doi:10.1109/fpt.2007.4439246 dblp:conf/fpt/GuneysuMP07 fatcat:d4c6vaoocrhmpb5f3w4mclsqna

Trustworthy Hardware [Scanning the Issue]

Ramesh Karri, Farinaz Koushanfar
2014 Proceedings of the IEEE  
gate arrays (FPGAs), microprocessors, and embedded systems.  ...  It presents design for trust techniques such as IC watermarking, fingerprinting, obfuscation, and split manufacturing. It presents 0018-9219  ...  hardware-based security protocols for digital rights management (DRM), IC metering, enabling and disabling, and authentication. Finally, it presents a variety of hardware-based attacks.  ... 
doi:10.1109/jproc.2014.2334837 fatcat:oifb7mphljhrhpdzbqfexw3h6y

A Flexible Design Flow for Software IP Binding in FPGA

Michael A. Gora, Abhranil Maiti, Patrick Schaumont
2010 IEEE Transactions on Industrial Informatics  
This work proposes a novel design flow for SWIP binding on a commodity FPGA platform lacking specialized hardcore security facilities.  ...  Software intellectual property (SWIP) is a critical component of increasingly complex field programmable gate arrays (FPGA)-based system-on-chip (SOC) designs.  ...  In this work, we propose an end-to-end design flow for binding a SWIP to a design based on a commodity FPGA.  ... 
doi:10.1109/tii.2010.2068303 fatcat:uqp4j6jztjag7koa7mvid3t37q

Analysis and Evaluation of PUF-Based SoC Designs for Security Applications

Alexandra Stanciu, Marcian N. Cirstea, Florin Dumitru Moldoveanu
2016 IEEE transactions on industrial electronics (1982. Print)  
The original method involved the conceptual design of adapted latch based PUFs and ring oscillator PUFs in combination with peripheral devices in order to create an environment for experimental analysis  ...  This paper presents a critical analysis and statistical evaluation of two categories of Physically Unclonable Functions (PUFs): ring oscillator PUF and a new proposed adapted latch based PUF.  ...  circuit on two different FPGA architectures without programmable delay lines; ii) a novel mechanism making the latch based PUF a good candidate for FPGA implementation; iii) an environment for the experimental  ... 
doi:10.1109/tie.2016.2570720 fatcat:xpkujudz5jeytfylfmli2qmxuu

FPGA Security: Motivations, Features, and Applications

Stephen M. Trimberger, Jason J. Moore
2014 Proceedings of the IEEE  
Motivated by specific threats, this paper describes FPGA security primitives from multiple FPGA vendors and gives examples of those primitives in use in applications.  ...  | Since their inception, field-programmable gate arrays (FPGAs) have grown in capacity and complexity so that now FPGAs include millions of gates of logic, megabytes of memory, high-speed transceivers,  ...  As with any design process, the design itself can be carried out in a secure location. Protection of IP during the design phase is no different for FPGAs than it is for ASICs or microprocessors.  ... 
doi:10.1109/jproc.2014.2331672 fatcat:qtwk2gqhzjfqjfjqvpptalop6m

Secure IP downloading for SRAM FPGAs

J. Castillo, P. Huerta, J.I. Martínez
2007 Microprocessors and microsystems  
This platform is based on the possibility offered by the new FPGA families for reprogramming part of the device while the rest is working.  ...  Nowadays there is a growing number of systems based on FPGAs spread over wide areas. When these kind of systems are used, serious security problems may appear.  ...  A commercial IP vendor can request a payment each time an FPGA is configured with its IP, or can demand a fee for each updated FPGA.  ... 
doi:10.1016/j.micpro.2006.02.001 fatcat:vnjs7gbo6rbedl7cmh6rpybzsy

SRAM-SUC: Ultra-Low Latency Robust Digital PUF [article]

Ayoub Mars, Hussam Ghandour, Wael Adi
2021 arXiv   pre-print
Hardware and software implementations show that the resulting SRAM-SUC has ultra-low latency compared to well-known PUF-based authentication mechanisms.  ...  In this paper, we propose a new practical mechanism for creating internally random ciphers in modern volatile and non-volatile SoC FPGAs, coined as SRAM-SUC.  ...  NOVEL PRACTICAL CONCEPT FOR SUC CREATION FOR ULTRA-LOW LATENCY AUTHENTICATION A.  ... 
arXiv:2106.07105v1 fatcat:aq5hshyj4nfu7eyxfxj4ml74sm

Hardware-Intrinsic Multi-Layer Security: A New Frontier for 5G Enabled IIoT

Hussain Al-Aqrabi, Anju P. Johnson, Richard Hill, Phil Lane, Tariq Alsboui
2020 Sensors  
A crucial aspect of this is to securely authenticate complex transactions between IIoT devices, whilst marshalling adversarial requests for system authorisation, without the need for a centralised authentication  ...  In this article we combine Physically Unclonable Function (PUF) hardware (using Field Programmable Gate Arrays—FPGAs), together with a multi-layer approach to cloud computing from the National Institute  ...  There exists a PUF for every authenticated user. PUF P ij represents the identity of the user i in the cloud layer j.  ... 
doi:10.3390/s20071963 pmid:32244458 pmcid:PMC7180754 fatcat:4pjnx7comzf6xbfja4ktym2l2e

Special issue on real time biometrics and secure media

Christos Grecos, Ahmed Bouridane
2013 Journal of Real-Time Image Processing  
The implementation benchmark of the AFAS either as a pure software approach on a PC platform under a dualcore processor (Intel Core 2 Duo T5600 at 1.83 GHz) or as a reconfigurable FPGA co-design (identical  ...  Fons et al. propose an FPGA architecture for an automatic fingerprint authentication system (AFAS).  ...  The implementation benchmark of the AFAS either as a pure software approach on a PC platform under a dualcore processor (Intel Core 2 Duo T5600 at 1.83 GHz) or as a reconfigurable FPGA co-design (identical  ... 
doi:10.1007/s11554-013-0369-7 fatcat:6lsfp6jh7nd6tohdlp4gbzkfhe

Brand and IP protection with physical unclonable functions

Jorge Guajardo, Sandeep S. Kumar, Geert-Jan Schrijen, Pim Tuyls
2008 2008 IEEE International Symposium on Circuits and Systems  
They can be turned into a useful tool to generate very secure secret keys in ICs and to provide keys to protect valuable IP of fabless IC companies, IP Vendors and design houses.  ...  In this paper we provide an overview of Physical Unclonable Functions and explain why they are a very valuable technology to protect a company's IP and hence at the same time its brand.  ...  The basic idea in Figure 5 is to use the PUF [7] with fully trusted TTP as a source for secret-key material, both for encryption and MAC-based authentication.  ... 
doi:10.1109/iscas.2008.4542135 dblp:conf/iscas/GuajardoKST08 fatcat:btue2qus7zg2nc5cff2uzmes5q

Transforming write collisions in block RAMs into security applications

Tim Guneysu, Christof Paar
2009 2009 International Conference on Field-Programmable Technology  
In this paper, we present a novel strategy to identify and authenticate FPGAs in applications using intrinsic, device-specific information (also known as Physically Unclonable Functions).  ...  In addition to applications for chip identification and authentication, we also propose a solution to efficiently create secret keys on-chip.  ...  One approach is to ship all FPGAs to the IP owner for on-site key installation, a smarter idea is presented in [8] based on a public-key based protocol.  ... 
doi:10.1109/fpt.2009.5377631 dblp:conf/fpt/GuneysuP09 fatcat:mo4dqfbpgngk5hsvepttrxpdvq

A novel PUF-based encryption protocol for embedded System on Chip

Alexandra Stanciu, Florin Dumitru Moldoveanu, Marcian Cirstea
2016 2016 International Conference on Development and Application Systems (DAS)  
This paper presents a novel security mechanism for sensitive data stored, acquired or processed by a complex electronic circuit implemented as System-on-Chip (SoC) on an FPGA reconfigurable device.  ...  The proposed new method is based on encrypted and authenticated communications between the microprocessor cores, FPGA fabric and peripherals inside the SoC.  ...  The use of the Ring Oscillator PUF and the latch based PUF to generate a unique identifier for FPGA devices are validated through the results obtained.  ... 
doi:10.1109/daas.2016.7492566 fatcat:3irwp74mafhtpazaqbhvzepeu4

ShEF: Shielded Enclaves for Cloud FPGAs [article]

Mark Zhao, Mingyu Gao, Christos Kozyrakis
2021 arXiv   pre-print
We describe a prototype implementation of ShEF for existing cloud FPGAs and measure the performance benefits of customizable security using five accelerator designs.  ...  We present ShEF, a trusted execution environment (TEE) for cloud-based reconfigurable accelerators.  ...  For encryption, we present two types of AES modules with 4x or 16x parallelism in the S-box (Section V). For authentication, we provide a SHA-256 HMAC module, as well as a PMAC module based on AES.  ... 
arXiv:2103.03500v1 fatcat:w7f2cnp3bneirhxeyfiiivw7my
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