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Nimeesha, Shikha Soni, Vandana Niranjan, Ashwni Kumar
2018 ICTACT Journal on Microelectronics  
The conclusion of this work is that there is a notable enhancement in slew rate, settling time and power dissipation in proposed adaptive biasing techniques.  ...  This paper presents a new adaptive biasing technique for improving the slew rate of CMOS opamps without increasing the power consumption.  ...  Hence, new novel circuits and techniques may be required in low-power analog circuits.  ... 
doi:10.21917/ijme.2018.0097 doaj:d5a6c40d8fd448f2ab83ae7e17a68de0 fatcat:rbfqcl2lcfelrbrk4jghz7tjaq

A micropower delta-sigma modulator based on a self-biased super inverter for neural recording systems

Le Wang, Luke Theogarajan
2010 IEEE Custom Integrated Circuits Conference 2010  
This paper presents a micropower, supply scalable 2 nd order delta-sigma modulator based on a novel self-biased fully differential super inverter for neural recording systems.  ...  The prototype modulator is implemented in a 0.13 µm CMOS process and occupies 0.03 mm 2 chip area.  ...  Acknowledgement The authors gratefully acknowledge MOSIS, especially Wes Hansford, for support through chip fabrication.  ... 
doi:10.1109/cicc.2010.5617454 dblp:conf/cicc/WangT10 fatcat:hoeud2joyraffd4u7rvz223ofm

2020 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 67

2020 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
., +, TCSI July 2020 2455-2466 Slewing Mitigation Technique for Switched Capacitor Circuits.  ...  ., +, TCSI March 2020 1069-1078 Slewing Mitigation Technique for Switched Capacitor Circuits.  ...  ., +, TCSI Dec. 2020 4295-4308 Enhanced Linearity in FD-SOI CMOS Body-Input Analog Circuits -Application to Voltage-Controlled Ring Oscillators and Frequency-Based ΣΔ ADCs.  ... 
doi:10.1109/tcsi.2021.3055003 fatcat:kbmst5td2bbvtl7vpbj3knnkri

Architectural Advancement of Digital Low-Dropout Regulators

Muhammad Abrar Akram, In-Chul Hwang, Sohmyung Ha
2020 IEEE Access  
In addition, it exhibits the fastest settling time of < 20 ns for a step load current of 500 mA/0.25 ns and achieves a peak current efficiency of 99.9 %. E.  ...  The DLDO using a dynamic-gain control scheme and all-digital auto-tuning engine [93] also achieves sub-cycle transient responses and demonstrates 55 ns of transient response time for a load current step  ...  His current research interests include the design of lowpower mixed-signals CMOS integrated circuits for mm-scaled implantable devices. Dr.  ... 
doi:10.1109/access.2020.3012467 fatcat:qpkm4ix7nbaopfwr4zr3nmx2a4

2018 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 65

2018 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
., and Pandey, N  ...  ., +, TCSI June 2018 2005-2014 Operational Transconductance Amplifier With Class-B Slew-Rate Boosting for Fast High-Performance Switched-Capacitor Circuits.  ...  ., +, TCSI Nov. 2018 3707-3719 Operational Transconductance Amplifier With Class-B Slew-Rate Boost- ing for Fast High-Performance Switched-Capacitor Circuits.  ... 
doi:10.1109/tcsi.2019.2896877 fatcat:3lzpngw2ofdjhiculf7ehrjeam

2020 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 67

2020 IEEE Transactions on Circuits and Systems - II - Express Briefs  
Islam, S., see 1464-1468 Ismail, A., and Sandell, M., A Novel Dynamic Detection for Flash Memory; 600-604 Issakov, V., see Aguilar, E., TCSII May 2020 906-910 Iu, H.H., see Lai, Q., 1129-1133 Iu,  ...  Sait, H., Design of a Single Chip PWM Driver Circuit for Inverter Welding Power Source; TCSII April 2020 720-724 Jacobsson, S., see Castaneda, O., TCSII May 2020 891-895 Jafari, E., and Binazadeh, T  ...  ., +, TCSII Sept. 2020 1609-1613 A Slew Rate Enhanced 2 x VDD I/O Buffer With Precharge Timing Technique.  ... 
doi:10.1109/tcsii.2020.3047305 fatcat:ifjzekeyczfrbp5b7wrzandm7e

A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR

Jipeng Li, Gil-Cho Ahn, Dong-Young Chang, Un-Ku Moon
2005 IEEE Journal of Solid-State Circuits  
The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping.  ...  The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a twochannel ADC architecture.  ...  This work was supported by the NSF Center for Design of Analog-Digital Integrated Circuits (CDADIC), NSF CAREER grant CCR-0133530, and partly by Analog Devices.  ... 
doi:10.1109/jssc.2004.842866 fatcat:citdjgk4argy5b6k5mvpkyiooe

CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

Mohammad Arif Sobhan Bhuiyan, Md. Rownak Hossain, Khairun Nisa' Minhad, Fahmida Haque, Mohammad Shahriar Khan Hemel, Omar Md Dawi, Mamun Bin Ibne Reaz, Kelvin J. A. Ooi
2022 Electronics  
, are framed, which will serve as a comparative study and reference for researchers.  ...  Systems-on-Chip's (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today's devices.  ...  The second stage CFA helps in minimizing the settling time of output and reducing the slew rate. On the other hand, accuracy is obtained in a steady-state by the global voltage-mode feedback.  ... 
doi:10.3390/electronics11020193 fatcat:d6c3zifp3vexzjixalmupuqgfy

A Power-Efficient Pipelined ADC with an Inherent Linear 1-Bit Flip-Around DAC

Wan, Su, Zhang, Chen
2020 Electronics  
Fabricated in a 0.13-μm CMOS process, the prototype ADC achieves a measured signal-to-noise plus distortion ratio (SNDR) of 66.4 dB and a spurious-free dynamic range (SFDR) of 76.7 dB at 20 MS/s sampling  ...  The ADC dissipates 5.2 mW of power and occupies an active area of 0.44 mm2.  ...  Acknowledgments: The authors would like to thank Skyrelay for the support of silicon fabrication. Conflicts of Interest: The authors declare no conflicts of interest.  ... 
doi:10.3390/electronics9010199 fatcat:kjlwhmdn7vgila54566fn2tutq

An Ultra Low-Voltage and Low-Power OTA Using Bulk-Input Technique and Its Application in Active-RC Filters

Arash Ahmadpour
2011 Circuits and Systems  
The OTA was designed in 90 nm CMOS process and operates at a single supply voltage of 0.5 V.  ...  Using a two-path bulk-driven OTA by the combination of two different amplifiers the DC gain and speed of the OTA is increased.  ...  Also, the corresponding author wishes to thank Reviewers for their useful comments and suggestions.  ... 
doi:10.4236/cs.2011.23026 fatcat:tm34toxux5fwde4abqycjk54ny

A Highly Reliable, 5.8 GHz DSRC Wake-Up Receiver with an Intelligent Digital Controller for an ETC System

Imran Ali, Muhammad Asif, Muhammad Riaz Ur Rehman, Danial Khan, Huo Yingge, Sung Jin Kim, YoungGun Pu, Sang-Sun Yoo, Kang-Yoon Lee
2020 Sensors  
It is fully synthesizable and needs 809 gates for its implementation in a 130 nm CMOS process with a 94 × 82 µm2 area.  ...  For accommodating wake-up signal frequency variation and enhancing WuRx accuracy, a digital hysteresis is incorporated.  ...  It is composed of a positive feedback circuit with an amplifier, AMP. A two stage amplifier with output inverter [31] is used as a low power CMOS amplifier.  ... 
doi:10.3390/s20144012 pmid:32707685 fatcat:hfgg2oq5wbam5a2lf4543fpsky

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

Xuqiang Zheng, Zhijun Wang, Fule Li, Feng Zhao, Shigang Yue, Chun Zhang, Zhihua Wang
2016 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end  ...  Moreover, a partial non-overlapping clock scheme associated with a highspeed reference buffer and fast comparators is proposed to maximize the residue settling time.  ...  Therefore, this non-overlapping time can be eliminated to increase the settling time of the residue amplification.  ... 
doi:10.1109/tcsi.2016.2580703 fatcat:js6rybr4pjf63plxzgqop6w7ja

A 2.5-V 57-MHz 15-Tap SC Bandpass Interpolating Filter With 320-MS/s Output for DDFS System in 0.35->tex<$mu hboxm$>/tex<CMOS

S.-P. U, R.P. Martins, J.E. Franca
2004 IEEE Journal of Solid-State Circuits  
The prototype ICs present a signal-to-noise-and-distortion ratio (SNDR) of 61 dB, with a dynamic range of 69 dB, for 1% THD, and 61 dB, for 1% IM3.  ...  At the same time, it translates 22-24 MHz input signals at 80 MS/s, to the frequency range of 56-58 MHz in the output at 320 MS/s, allowing also a perfect operation at 400 MS/s, in 0.35-m CMOS technology  ...  ., for the technical support, and the reviewers for their useful comments and suggestions.  ... 
doi:10.1109/jssc.2003.820855 fatcat:shzm2tmlgvc2tjaalgn2jzd4iq

A segmented gate driver with adjustable driving capability for efficiency optimization

A. A. Fomani, W. T. Ng
2010 The 2010 International Power Electronics Conference - ECCE ASIA -  
Fomani A novel gate driver design is proposed to improve the conversion efficiency of DC-DC converters.  ...  Furthermore, in addition to efficiency improvements, a 60% reduction in the ringing and overshoot/undershoot was observed.  ...  The programmable slew rate technique [30] [31] in digital designs, also allows the control of the rise and fall time of the output signal.  ... 
doi:10.1109/ipec.2010.5543143 fatcat:oqeovterfnd7fd3nsumwxxavuq

A Novel Interface for Eddy Current Displacement Sensors

M.R. Nabavi, S. Nihtianov
2009 IEEE Transactions on Instrumentation and Measurement  
In this paper, we propose a novel interface concept for eddy current displacement sensors. A measurement method and a new front-end circuit are also proposed.  ...  The signal conditioning circuit utilizes a standard 0.35-μm complementary metal-oxide semiconductor (CMOS) technology.  ...  Based on the simulation results, this class AB scheme can enhance the slew rate of the opamp by about 50%.  ... 
doi:10.1109/tim.2009.2012945 fatcat:ggaasrbsyzh6thkpy27fye4w6u
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