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Architectural Support for Fault Tolerance in a Teradevice Dataflow System

Sebastian Weis, Arne Garbade, Bernhard Fechner, Avi Mendelson, Roberto Giorgi, Theo Ungerer
2014 International journal of parallel programming  
In this paper, we present a fault tolerant architecture for a coarse-grained dataflow system, leveraging the inherent features of the dataflow execution model.  ...  Furthermore, we exploit the dataflow execution model for a thread-level recovery scheme.  ...  Popovic for their initial studies on the DTA-C architecture and P. Faraboschi of HP for his precious suggestions and support on the COTSon simulator.  ... 
doi:10.1007/s10766-014-0312-y fatcat:kygdzmqyvrbonia2cu7n4glnsu

A Fault Detection and Recovery Architecture for a Teradevice Dataflow System

Sebastian Weis, Arne Garbade, Julian Wolf, Bernhard Fechner, Avi Mendelson, Roberto Giorgi, Theo Ungerer
2011 2011 First Workshop on Data-Flow Execution Models for Extreme Scale Computing  
Furthermore, we propose a recovery technique for dataflow threads.  ...  In this paper, we conceptualize a fault tolerant architecture for a scalable threaded dataflow system. We provide methods to detect permanent, intermittent, and transient faults during the execution.  ...  For simplicity we call a dataflow thread with micro control flow support a thread. Basic Architecture We assume a tiled hardware architecture, where a tile is denoted as a node.  ... 
doi:10.1109/dfm.2011.9 fatcat:lnfzesk64nhxdg32vv7zfclece

Realizing Efficient Execution of Dataflow Actors on Manycores

Essayas Gebrewahid, Mingkun Yang, Gustav Cedersjo, Zain Ul Abdin, Veronica Gaspes, Jorn W. Janneck, Bertil Svensson
2014 2014 12th IEEE International Conference on Embedded and Ubiquitous Computing  
Actor based dataflow languages are being considered as a programming model. In this paper we present a code generator for CAL, one such dataflow language.  ...  We propose to use a compilation tool with two intermediate representations. We start from a machine model of the actors that provides an ordering for testing of conditions and firing of actions.  ...  ACKNOWLEDGMENT The authors would like to thank Adapteva and Nethra Imaging Inc. for giving access to their software development suites and hardware boards.  ... 
doi:10.1109/euc.2014.55 dblp:conf/euc/GebrewahidYCAGJS14 fatcat:dr7ic562y5fvdorgk3zsvrpyui

CLAM

Xavier Amatriain, Pau Arumi, David Garcia
2006 Proceedings of the 14th annual ACM international conference on Multimedia - MULTIMEDIA '06  
These commonalities are expressed in the form of a metamodel for multimedia processing systems and a design pattern language.  ...  In this article, we present CLAM, a C++ software framework, that offers a complete development and research platform for the audio and music domain.  ...  A non-exhaustive list of contributors should at least include Maarten de Boer, Miguel Ramírez, Xavi Rubio, Ismael Mosquera, Xavier Oliver, Enrique Robledo, and our students from the Google Summer of Code  ... 
doi:10.1145/1180639.1180847 dblp:conf/mm/AmatriainAG06 fatcat:kk7qbisigvebdf7hssuy7al3pi

A framework for efficient and rapid development of cross-platform audio applications

Xavier Amatriain, Pau Arumi, David Garcia
2007 Multimedia Systems  
These commonalities are expressed in the form of a metamodel for multimedia processing systems and a design pattern language.  ...  In this article, we present CLAM, a C++ software framework, that offers a complete development and research platform for the audio and music domain.  ...  A non-exhaustive list of contributors should at least include Maarten de Boer, Miguel Ramírez, Xavi Rubio, Ismael Mosquera, Xavier Oliver, Enrique Robledo, and our students from the Google Summer of Code  ... 
doi:10.1007/s00530-007-0109-6 fatcat:3tenfm4syfhp3mr6nzqabig4f4

Co-synthesis of a configurable SoC platform based on a network on chip architecture

Mário P. Véstias, Horácio C. Neto
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
In this paper, we propose an approach to the design space exploration of a configurable SoC (CSoC) platform based on a network on chip (NoC) architecture for the execution of dataflow dominated embedded  ...  The approach has been validated with the design of a color image compression algorithm in an FPGA.  ...  Switching is the mechanism that removes data from an input channel of a router and places it on an output channel, while arbitration is responsible for scheduling the access to channels and buffers.  ... 
doi:10.1145/1118299.1118312 fatcat:bcsrk7psorhe5aj3qzm2ehpzpm

Monotonicity and run-time scheduling

Maarten H. Wiggers, Marco J.G. Bekooij, Gerard J.M. Smit
2009 Proceedings of the seventh ACM international conference on Embedded software - EMSOFT '09  
Given that the inter-task synchronisation of the application allows for a dataflow model that is functionally deterministic, this enables exploration of various buffer capacities and scheduler settings  ...  Typically, these applications are partitioned into tasks that communicate over buffers together forming a task graph.  ...  In all experiments, we consider an architecture with 2 ARM7 processors [1] that are directly connected to a double-ported memory. All instructions and (shared) data are in this memory.  ... 
doi:10.1145/1629335.1629359 dblp:conf/emsoft/WiggersBS09 fatcat:pmj2dpdbzfgb7niv3kwggzkupq

ATLAS TDAQ dataflow network architecture analysis and upgrade proposal

S. Stancu, M. Ciobotaru, K. Korcyl
2005 14th IEEE-NPSS Real Time Conference, 2005.  
Based on performance, fault tolerance and flexibility considerations a preferred architecture is proposed for implementation.  ...  We introduce the use of 10 Gigabit Ethernet as a flexible and simple technology for concentrating traffic.  ...  ACKNOWLEDGMENT The authors would like to express their gratitude to the ATLAS TDAQ collaboration for providing constant support and feedback that guided our work.  ... 
doi:10.1109/rtc.2005.1547531 fatcat:4sl2gvrpzzefbpheqxyyhiscsa

ATLAS TDAQ DataFlow network architecture analysis and upgrade proposal

S. Stancu, M. Ciobotaru, K. Korcyl
2006 IEEE Transactions on Nuclear Science  
Based on performance, fault tolerance and flexibility considerations a preferred architecture is proposed for implementation.  ...  We introduce the use of 10 Gigabit Ethernet as a flexible and simple technology for concentrating traffic.  ...  ACKNOWLEDGMENT The authors would like to express their gratitude to the ATLAS TDAQ collaboration for providing constant support and feedback that guided our work.  ... 
doi:10.1109/tns.2006.873302 fatcat:676s67mm2fcijh4n57wm6c7uzi

Parallel volume visualization on a hypercube architecture

C. Montani, R. Perego, R. Scopigno
1992 Proceedings of the 1992 workshop on Volume visualization - VVS '92  
A hybrid strategy to my tracing parallelitation is applied, using ray-dataflow within an image partition approach.  ...  Baaed on the ray tracing (RT) uiaualization technique, the system works on a distributed memory MIMD architecture.  ...  The authors also thank Paolo Bussetti and Luca Misericordia for their valuable contribution to the system implementation.  ... 
doi:10.1145/147130.147139 dblp:conf/vvs/MontaniPS92 fatcat:iuzzofrseradhllzvstbncboxq

Dataflow programming model for reconfigurable computing

L. Gantel, A. Khiar, B. Miramond, A. Benkhelifa, F. Lemonnier, L. Kessal
2011 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)  
This paper focuses on the complex problem of communication management between software and hardware actors for dataflow oriented processing, and proposes solutions to leverage this issue.  ...  This paper addresses the problem of image processing algorithms implementation onto dynamically and reconfigurable architectures.  ...  It is composed of a standard double port memory in which the thread can write the identifier of a system call and its parameters.  ... 
doi:10.1109/recosoc.2011.5981505 dblp:conf/recosoc/GantelKMBLK11 fatcat:qrzndvvqove4pkyxrlnayj5b2e

A component-based framework for the Cell Broadband Engine

Timothy D. R. Hartley, Umit V. Catalyurek
2009 2009 IEEE International Symposium on Parallel & Distributed Processing  
-Techniques to deal with the small memories of the Synergistic Processor Elements, such as double-buffering. -Distributed memory programming models. • The developer's own domain of expertise.  ...  This initial DataCutter-Lite implementation defines a powerful, but simple abstraction for carrying out complex computations in a filter-stream model.  ...  Therefore, DCL uses prefetches buffers when calling filters' processing functions. In the simplest case, this allows automatic double-buffering of data for use in streaming operations.  ... 
doi:10.1109/ipdps.2009.5160919 dblp:conf/ipps/HartleyC09 fatcat:s7v3yo4ybvbp7mx3t3sh6tvjxe

TTADF: Power Efficient Dataflow-Based Multicore Co-Design Flow

Ilkka Hautala, Jani Boutellier, Olli Silven
2019 IEEE transactions on computers  
This work presents a dataflow-based co-design framework TTADF that reduces the design effort of both software and hardware design for mobile processing platforms.  ...  The results of the TTADF co-design-based solutions are compared against previous manually created designs and a recent dataflow-based design flow, showing that TTADF provides very high energy efficiency  ...  The FIFO capacity is also set to two to enable double buffering.  ... 
doi:10.1109/tc.2019.2937867 fatcat:bkhi52rqkbhivdvtffztgp2424

Transformations of High-Level Synthesis Codes for High-Performance Computing [article]

Johannes de Fine Licht, Maciej Besta, Simon Meierhans, Torsten Hoefler
2020 arXiv   pre-print
We show how these can be used to efficiently exploit pipelining, on-chip distributed fast memory, and on-chip dataflow, allowing for massively parallel architectures.  ...  To alleviate this, we present a collection of optimizing transformations for HLS, targeting scalable and efficient architectures for high-performance computing (HPC) applications.  ...  To move data between PEs, communication channels with a handshake mechanism are used. These channels double as synchronization points, as they imply a consensus on the program state.  ... 
arXiv:1805.08288v6 fatcat:rklumgxixbg2dfglgwcfrxd3se

Efficient execution of memory access phases using dataflow specialization

Chen-Han Ho, Sung Jin Kim, Karthikeyan Sankaralingam
2015 SIGARCH Computer Architecture News  
This paper identifies a new opportunity for improving the efficiency of a processor core: memory access phases of programs.  ...  Such an engine can serve as a general way for any accelerator to execute its respective induced phase, thus providing a common interface and implementation for current and future accelerators.  ...  Support for this research was provided by NSF under the following grants CCF-1162215, CNS-1228782, CNS-1218432.  ... 
doi:10.1145/2872887.2750390 fatcat:c2malodvtfcxjn2uxmowb5heci
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