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Virtex 4 FPGA Implementation of Viterbi Decoded 64-bit RISC for High Speed Application using Xilinx
2014
International Journal of Computer Applications
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In the modern era of electronics and communication decoding and encoding of any data(s) using VLSI technology requires low power, less area and high speed constrains. ...
Thirdly, all the viterbi decoders are compared, simulated, synthesized and the proposed approach shows the best simulation and synthesize results for low power and high speed application in VLSI design ...
Song Li and Qing-Ming Yi (2006) proposed a scheme based on Verilog language for the implementation of high-speed and low power consumption bi-directional viterbi decoder [3] . ...
doi:10.5120/15422-4011
fatcat:vubn5z3umvaclhdrlsudc432aq
Implementation of scalable power and area efficient high-throughput Viterbi decoders
2002
IEEE Journal of Solid-State Circuits
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Additional new concepts allow building a signal-flow graph suitable for the design of high-speed Viterbi decoders with low power. ...
Using a flexible datapath generator facilitates the essential quantitative optimization from architectural down to physical level to fully exploit the low-power and high-speed potential of a given technology ...
Gierenz for his contributions, and L. Gazsi and F. Frieling of Infineon Technologies for valuable discussions and for their cooperation. ...
doi:10.1109/jssc.2002.1015694
fatcat:apsazi2kkrac3panqorqu3gh7u
A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering
2009
International Journal of Communications, Network and System Sciences
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A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. ...
Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved ...
A bidirectional Viterbi decoder that can meet the requirements of high-speed and low power consumption has been discussed by Song Li [2] . ...
doi:10.4236/ijcns.2009.26064
fatcat:jbgddownu5fubkplomirw3labu
A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique
2010
2010 IEEE Asia Pacific Conference on Circuits and Systems
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A low-power radix-4 Viterbi decoder based on a differential cascode voltage switch with pass gate (DCVSPG) pulsed latch with sharing technique is proposed to process two bits concurrently. ...
With a Viterbi decoder, the bit error probability of a communication system can be reduced. However, the power consumption of exploiting Viterbi decoder is an overhead to systems. ...
The Viterbi decoder is a popular decoder for its high-speed and low-cost properties, and it has been adopted by many standards, for example, ultra-wide band (UWB) system and Wi-Fi. ...
doi:10.1109/apccas.2010.5774991
dblp:conf/apccas/LeeCL10
fatcat:l2zhqath45gzrepoeszcnfd3yy
Speed optimization of a FPGA based modified viterbi decoder
2013
2013 International Conference on Computer Communication and Informatics
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Advancement in the VlSI technology using low power, less area and high speed constraints is mostly used for encoding and decoding of data. ...
Viterbi decoder uses viterbi algorithm for TCM decoding, but the efficient speed and power reduction is not achieved at the receiving ends. ...
LOW-POWER HIGH-SPEED VITERBI DECODER DESIGN We are still using the 4-D8PSK TCM system as described in [2] as example. ...
doi:10.1109/iccci.2013.6466245
fatcat:ct23tklchreyfp3amkgueqlssa
Low-power asynchronous viterbi decoder for wireless applications
2004
Proceedings of the 2004 international symposium on Low power electronics and design - ISLPED '04
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This paper describes the implementation of an asynchronous 64state, 1/2-rate Viterbi decoder using an original architecture and design methodology. ...
The choice of an asynchronous design was predicated by the power and speed advantages of such a methodology. ...
Such portable, battery operated systems, require low-power consumption as well as high processing speeds, over 100 Mb/s, to allow multimedia transmission. ...
doi:10.1145/1013235.1013306
dblp:conf/islped/KawokgyS04
fatcat:32at47cqrfdctktirb7wy6iyyi
An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates
2015
The Scientific World Journal
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For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. ...
The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz. ...
Fast developments in the field of communication in the recent years have created a rising demand for high speed and low power Viterbi decoders with extended battery life, low power dissipation, and low ...
doi:10.1155/2015/621012
pmid:26558289
pmcid:PMC4617693
fatcat:asyw6jkco5cb3g6oqwbfhaimtm
An Efficient Low Power Viterbi Decoder Design using T-algorithm
2013
International Journal of Computer Applications
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The architecture which reduces the complexity and power Consumption by as much as 70% without effecting the decoding speed. ...
This paper presents an efficient Low-Power Viterbi Decoder Design using T-algorithm. ...
CONCLUSION We have proposed an efficient low power Viterbi decoder design using T-algorithm which reduces the power consumption and complexity of the Viterbi decoder without reducing the clock speed. ...
doi:10.5120/13246-0707
fatcat:3oszzjpq6rglte5dz3bz36akoe
Implementation of Viterbi Decoder using T-algorithm for TCM Decoders
English
2015
IJIREEICE
English
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Viterbi Decoder employed in digital wireless communication plays a dominant role in overall power consumption of trellis coded modulation (TCM) decoder. ...
The proposed Viterbi Decoder (VD) implementation can reduce the power consumption with less reduction in the maximum decoding speed. ...
VITERBI DECODER DESIGN FOR HIGH SPEED LOW POWER BER performance of a 4-D 8PSK TCM system [2] [5] with code rate (k/n) 3/4 is almost same as the conventional T-algorithm, since the precomputation algorithm ...
doi:10.17148/ijireeice.2015.3539
fatcat:e5y7u6pp5vcbbg47yqpj6tdvy4
Implementation of Low-Power Adaptive Viterbi Decoder for Wireless Communication
2015
International Journal on Communications Antenna and Propagation
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Thus this paper presents the design of an Adaptive Viterbi Decoder (AVD) that uses survivor path with parameters in an attempt to reduce the power and cost and at the same time increase in speed. ...
Most of the researches aimed to reduce power consumption or work with high frequency for using the decoder in the modern applications such as 3 GPP, DVB, and wireless technology. ...
"Survivor Path Processing in Viterbi Decoders" presented a new class of hybrid survivor path architecture based on Register exchange and Trace back concepts. ...
doi:10.15866/irecap.v5i6.7421
fatcat:vau5w2nus5djhphclswf54geqq
Power efficient Viterbi decoder based on pre-computation technique for portable digital multimedia broadcasting receiver
2007
IEEE transactions on consumer electronics
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So, it is desired to design a high speed and low-power hardware scheme for viterbi decoder. ...
Index Terms -Digital multimedia, broadcasting (DMB), viterbi decoder, pre-computation, low-power. Dong-Sun Kim (M'99) was born in Incheon, Korea, in 1972. ...
The left square of Fig. 8 is applied by pre-computation and decomposition method for low-power consumption and the right square of Fig. 8 represents a new PMN architecture for performing high-speed ...
doi:10.1109/tce.2007.381700
fatcat:5hxkcsfc4je2he4ou5bxr7a3d4
High-Speed Low-Power Viterbi Decoder Design for TCM Decoders
2012
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. ...
We propose a pre-computation architecture incorporated with -algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. ...
As a result, the decoding speed of the low-power VD is greatly improved. ...
doi:10.1109/tvlsi.2011.2111392
fatcat:l426uv3emfaqhkq3jmh572jw4e
A FEC Architecture for UWB System
2006
IEEE Vehicular Technology Conference
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This RS decoder has low latency and small area using simple and regular processing elements for the key equation solve block. ...
The estimated hardware size of the Viterbi decoder is 120k gates and the clock frequency is 144MHz. The proposed Reed-Solomon decoder uses a modified euclidean algorithm to solve a key equation. ...
To implement this Viterbi decoder, a very high speed operation clock is needed. ...
doi:10.1109/vtcf.2006.309
dblp:conf/vtc/ChoiCL06
fatcat:igjjynklrvd6lbpmt576w5m2xq
Study of heterogeneous and reconfigurable architectures in the communication domain
2003
Advances in Radio Science
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An implementation on an embedded FPGA kernel is in between these two representing an attractive compromise with high flexibility and low power consumption. ...
Flexibility of modern architectures is desirable, e.g. concerning adaptation to new standards and reduction of time-to-market of a new product. ...
Applying quantitative optimisation on all levels of design hierarchy two Viterbi decoders were designed (Gemmeke et al., 2002) : one optimised for high speed operation, the other for low power dissipation ...
doi:10.5194/ars-1-165-2003
fatcat:wqaohyjkuzaibkbq443ixry4lm
Designing of precomputational-based low-power Viterbi decoder
2004
Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication (IEEE Cat. No.04EX710)
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This work presents a precomputation-based low power design scheme, which can also be applied to high-speed V D design, to perform the low-power ACSU is a collection of butterflies' calculations. ...
CONCLUSIONS Low-power architectures for the ACSU of VD were presented. ...
doi:10.1109/casset.2004.1321960
fatcat:gvyijnfexfcuxnxb5b3tsjbblm
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