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A new gate delay model for simultaneous switching and its applications

Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
2001 Proceedings of the 38th conference on Design automation - DAC '01  
We present a new model to capture the delay phenomena associated with simultaneous to-controlling transitions.  ...  The proposed delay model accurately captures the effect of the targeted delay phenomena over a wide range of transition times and skews.  ...  PROPOSED DELAY MODEL In this paper we propose a new delay model to handle simultaneous to-controlling transitions.  ... 
doi:10.1145/378239.378488 dblp:conf/dac/ChenGB01 fatcat:ttoyxdxkhnd4lcpt2fchjw2z7q

A new gate delay model for simultaneous switching and its applications

Liang-Chi Chen, S.K. Gupta, M.A. Breuer
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)  
We present a new model to capture the delay phenomena associated with simultaneous to-controlling transitions.  ...  The proposed delay model accurately captures the effect of the targeted delay phenomena over a wide range of transition times and skews.  ...  PROPOSED DELAY MODEL In this paper we propose a new delay model to handle simultaneous to-controlling transitions.  ... 
doi:10.1109/dac.2001.935522 fatcat:as6i7ncudrcqdiqqcci2whrjka

Gate sizing in the presence of gate switching activity and input vector control

Nathaniel A. Conos, Saro Meguerdichian, Miodrag Potkonjak
2013 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)  
As dictated by the new objective function, our algorithm conducts iterative gate freezing and unlocking with cut-based search for the most beneficial gate sizes under delay constraints.  ...  We introduce a novel gate sizing approach that considers both the gate switching activity (SA) and gate input vector control leakage (IVC).  ...  We use a cell table library look-up as [4] to model gate rise and f all delay (dl r,f ) as a function of its input slew (transition time), and driving load.  ... 
doi:10.1109/vlsi-soc.2013.6673265 dblp:conf/vlsi/ConosMP13 fatcat:x3pbwf7on5epvj5opvwv6klr4m

Gate Sizing Under Uncertainty [chapter]

Nathaniel A. Conos, Saro Meguerdichian, Miodrag Potkonjak
2015 IFIP Advances in Information and Communication Technology  
Our algorithm conducts iterative gate freezing and unlocking with cut-based search for the most beneficial gate sizes under delay constraints.  ...  We present a gate sizing approach to efficiently utilize gate switching activity (SA) and gate input vector control leakage (IVC) uncertainty factors in the objective function in order enable more efficient  ...  We use a cell table library look-up as [5] to model gate rise and f all delay (dl r, f ) as a function of its input slew (transition time), and driving load.  ... 
doi:10.1007/978-3-319-23799-2_2 fatcat:22oibkhp3rbyvbpu3ulyrg5554

Simultaneous voltage scaling and gate sizing for low-power design

Chunhong Chen, M. Sarrafzadeh
2002 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
This paper presents a new approach using simultaneous voltage-scaling and gate-sizing for low power without violating the timing constraints.  ...  We provide the problem formulation in this application, and propose algorithms for single voltagescaling, single gate-sizing, and their simultaneous manipulation.  ...  ACKNOWLEDGMENT The authors would like to thank the anonymous reviewers for their comments which improved the quality of the paper.  ... 
doi:10.1109/tcsii.2002.802964 fatcat:wffxsqpcjja6jk5hmip37dfffy

Event-driven simulation of digital circuits using modified Petri nets algorithm

Alexander Lapin, Dmitry Bulakh, Yuriy Vagapov
2017 2017 Internet Technologies and Applications (ITA)  
This paper presents a modified Petri nets simulation algorithm applied as an engine for a logic simulator in digital integrated circuit design.  ...  The simulator uses an eventdriven algorithm and eliminates the delta delay which occurs in the majority of modern simulation algorithms.  ...  Obviously, the simulation program cannot evaluate the simultaneous switching of several gates so therefore it implements a "delta delay" algorithm to perform the sequential switching of inputs C and EC  ... 
doi:10.1109/itecha.2017.8101903 fatcat:a57oxkpxmzcldj4o4h5fhhtuxa

Power consumption in XOR-based circuits

Y. Ye, K. Roy, R. Drechsler
1999 Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)  
Due to di erent possible implementations of XOR gate, we model the XOR gate as a basic gate and a complex static CMOS gate, respectively.  ...  We i n v estigate the suitability of using di erent delay models such as unit delay, fanout delay, and random delay i n p o w er estimation of XOR dominated logic.  ...  Acknowledgment This research was supported by DARPA F33615-95-C-1625 and NSF CAREER award 9501869-MIP.  ... 
doi:10.1109/aspdac.1999.760018 dblp:conf/aspdac/YeRD99 fatcat:wryq3kwscbbt3fugyx352ngszq

Transistor sizing issues and tool for multi-threshold CMOS technology

James Kao, Anantha Chandrakasan, Dimitri Antoniadis
1997 Proceedings of the 34th annual conference on Design automation conference - DAC '97  
This paper describes some of the issues involved in sizing transistors for MTCMOS and also introduces a variable breakpoint switch level simulator that can rapidly calculate delay in MTCMOS circuits as  ...  functions of design variables such as Vdd, V" and sleep transistor sizing.  ...  Simple Model For MTCMOS Propagation Delay To model the effects of MTCMOS on circuit delay, it is useful to consider the delay of an inverter when N-I other inverters are simultaneously switching through  ... 
doi:10.1145/266021.266182 dblp:conf/dac/KaoCA97 fatcat:2fa6vcebkzeafb6xil3cpjby3a

New Ternary Data Encoding for Delay-Insensitive Asynchronous Design

Je-Hoon Lee, Won-Ki Sung
2014 International Journal of Control and Automation  
This paper presents a new asynchronous ternary logics based on a new data-encoding scheme. The main aim of this research is to provide the flawless truth table for varying logic gates.  ...  A conventional B-ternary logic for an asynchronous design has many drawbacks, most notably its incomplete truth table of the basic logic gates.  ...  Thus, it is applicable for asynchronous circuit employing SI delay model for low-energy consumption.  ... 
doi:10.14257/ijca.2014.7.1.16 fatcat:nqnywk5z2jhhhjysw5oeumxkqa

Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability

Hratch Mangassarian, Andreas Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
Finally, a number of optimization techniques, such as the use of gate switching equivalence classes, are described to improve the scalability of the proposed method.  ...  The proposed framework is enhanced to handle unit gate delays and output glitches. In order to disallow unrealistic input transitions, we show how to integrate input constraints in the formulation.  ...  The described framework is applicable to both combinational and sequential circuits, and to both zero and unit gate delay models. Glitches are accounted for in the unit gate delay formulation.  ... 
doi:10.1109/date.2007.364519 fatcat:sqctjrd7dvdlnkyzhiceev6h7m

Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability

Hratch Mangassarian, Andreas Veneris, Farid N. Najm
2012 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Finally, a number of optimization techniques, such as the use of gate switching equivalence classes, are described to improve the scalability of the proposed method.  ...  The proposed framework is enhanced to handle unit gate delays and output glitches. In order to disallow unrealistic input transitions, we show how to integrate input constraints in the formulation.  ...  The described framework is applicable to both combinational and sequential circuits, and to both zero and unit gate delay models. Glitches are accounted for in the unit gate delay formulation.  ... 
doi:10.1109/tcad.2011.2169259 fatcat:l6ld5dlocvgfvigaz7gd4ptwra

Accurate estimation of combinational circuit activity

Huzefa Mehta, Manjit Borah, Robert Michael Owens, Mary Jane Irwin
1995 Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95  
A formulation is presented in this paper which includes signal correlation and multiple gate input switching.  ...  However none of these techniques take i n to account circuit activity when two o r more inputs change simultaneously or when glitching occurs.  ...  The clock has a normalized switching density o f 1 e p v. In Zero delay model all gates are assumed to have zero delay and in unit delay model all gates have unit delay.  ... 
doi:10.1145/217474.217599 dblp:conf/dac/MehtaBOI95 fatcat:insfknpwqjddlilu3zm2d72zaq

Accurate Estimation of Combinational Circuit Activity

Huzefa Mehta
1995 Proceedings - Design Automation Conference  
A formulation is presented in this paper which includes signal correlation and multiple gate input switching.  ...  However none of these techniques take i n to account circuit activity when two o r more inputs change simultaneously or when glitching occurs.  ...  The clock has a normalized switching density o f 1 e p v. In Zero delay model all gates are assumed to have zero delay and in unit delay model all gates have unit delay.  ... 
doi:10.1109/dac.1995.250039 fatcat:7br3ocns6fcm5c5k46fpl2h7y4

Transition delay fault test pattern generation considering supply voltage noise in a SOC design

Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
2007 Proceedings - Design Automation Conference  
In this paper, we first present a case study of a SOC design and show detailed IR-drop analysis, measurement and its effects on design performance during at-speed test.  ...  A new practical pattern generation methodology is proposed to generate supply noise tolerant delay test patterns using existing capabilities in commercial ATPG tools.  ...  Section 2 explains a case study for a SOC design with detailed statistical and dynamic IR-drop analysis for at-speed test pattern application in addition to a new power model to measure the average switching  ... 
doi:10.1145/1278480.1278616 dblp:conf/dac/AhmedTJ07 fatcat:e746qjmmgvcwdphrco5hh7fsmq

Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design

Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
2007 Proceedings - Design Automation Conference  
In this paper, we first present a case study of a SOC design and show detailed IR-drop analysis, measurement and its effects on design performance during at-speed test.  ...  A new practical pattern generation methodology is proposed to generate supply noise tolerant delay test patterns using existing capabilities in commercial ATPG tools.  ...  Section 2 explains a case study for a SOC design with detailed statistical and dynamic IR-drop analysis for at-speed test pattern application in addition to a new power model to measure the average switching  ... 
doi:10.1109/dac.2007.375222 fatcat:lt7w5t5msnd2hk37lhzgjw7qwa
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