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A New FPGA/DSP-Based Parallel Architecture for Real-Time Image Processing

J Batlle
2002 Real-time imaging  
This architecture is structured with a two-dimensional (2D) array of FPGA/DSP-based reprogrammable processors P ij .  ...  This architecture has been designed to deal with parallel/pipeline procedures, performing operations which handle various simultaneous input images, and cover a wide range of real-time computer vision  ...  FPGA/DSP-BASED PARALLEL ARCHITECTURE 349 At instant T 3 : K The value of the entering byte changes from 20 to 30 h.  ... 
doi:10.1006/rtim.2001.0273 fatcat:gzpo6lpaongtfiuxd7ph5fvziy

Evolution of real-time onboard processing and classification of remotely sensed data

Mahendra H N
2020 Indian Journal of Science and Technology  
Objectives: To provide a technical review of current hardware architecture, techniques, problems, and practices used for real-time on-board data processing and classification of Remotely Sensed (RS) data  ...  These results aid the researchers to come up with a more optimized design and hardware architecture for data preprocessing and classification.  ...  Acknowledgement This research was supported by JSS Academy of Technical Education, Bangalore-560060 and Visvesvaraya Technological University -TEQIP, Jnana sangama, Belagavi-590018 for grant of financial  ... 
doi:10.17485/ijst/v13i20.459 fatcat:rv3okqtthjhefd3z2xwam3kazy

Dual Super-Systolic Core for Real-Time Reconstructive Algorithms of High-Resolution Radar/SAR Imaging Systems

Alejandro Castillo Atoche, Javier Vázquez Castillo
2012 Sensors  
A high-speed dual super-systolic core for reconstructive signal processing (SP) operations consists of a double parallel systolic array (SA) machine in which each processing element of the array is also  ...  In this study, we addressed the design of a high-speed dual super-systolic array (SSA) core for the enhancement/reconstruction of remote sensing (RS) imaging of radar/synthetic aperture radar (SAR) sensor  ...  In addition, the authors believe that the FPGA/DSP-based systems in aggregation with novel bit-level super-systolic architectures offer enormous computation potential in RS systems for newer Geospatial  ... 
doi:10.3390/s120302539 pmid:22736964 pmcid:PMC3376574 fatcat:rh3ohzgyabfvngoam3enitca6m

Embedded Vision System for Atmospheric Turbulence Mitigation

Ajinkya Deshmukh, Gaurav Bhosale, Swarup Medasani, Karthik Reddy, P. Hemantha Kumar, A. Chandrasekhar, P. Kiran Kumar, K. Vijayasagar
2016 2016 IEEE Conference on Computer Vision and Pattern Recognition Workshops (CVPRW)  
FPGA-DSP based embedded realization of our algorithm achieves nearly 15x speed-up along with lesser memory requirement over a quad core PC implementation.  ...  In this paper, we describe a real time embedded solution connected with traditional cameras to both rectify turbulence distortions and reliably detect and track true moving targets.  ...  This parallel interface is highly preferred for image processing applications as burst data (ex. complete image) can be transferred in quick time.  ... 
doi:10.1109/cvprw.2016.112 dblp:conf/cvpr/DeshmukhBMRKCKV16 fatcat:sr3lg6khzreitm3owxbggnz3iu

On-Board, Real-Time Preprocessing System for Optical Remote-Sensing Imagery

Baogui Qi, Hao Shi, Yin Zhuang, He Chen, Liang Chen
2018 Sensors  
Second, a co-processing system using a field-programmable gate array (FPGA) and a digital signal processor (DSP; altogether, FPGA-DSP) based on optimization is designed to realize real-time preprocessing  ...  In this paper, a real-time processing architecture for on-board imagery preprocessing is proposed.  ...  Second, we designed a parallel acceleration architecture for real-time requirements. An optical image preprocessing system that is based on a FPGA and DSP coprocessor was designed and implemented.  ... 
doi:10.3390/s18051328 pmid:29693585 pmcid:PMC5982232 fatcat:pw5xmzxmabhcvno3lthmazjpue

Front Matter: Volume 7130

Rongsheng Lu, Yetai Fei, Kuang-Chao Fan
2009 Fourth International Symposium on Precision Mechanical Measurements  
A unique, consistent, permanent citation identifier (CID) number is assigned to each article at the time of the first publication.  ...  Yang, Taiyuan Univ. of Technology (China) 7130 05 A new method to measure circular runout of end-milling spindle based on cutting mark [7130-04] J. Zhou, S.  ...  (Hong Kong, China) 7130 2Z The design and implementation of a flexible FPGA/DSP based architecture for real-time image processing [7130-106] X. Jia, H. Wang, X. Liu, Information Engineering Univ.  ... 
doi:10.1117/12.822011 fatcat:t5cdengapfg23prawodje4qsnq

MATLAB as a Design and Verification Tool for the Hardware Prototyping of Wireless Communication Systems [chapter]

Oriol Font-Bach, Antonio Pascual-Iserte, Nikolaos Bartzoudis, David Lopez
2012 MATLAB - A Fundamental Tool for Scientific Computing and Engineering Applications - Volume 2  
Real-time system-prototyping using FPGA devices is a painstaking and time-consuming process that goes beyond a controlled computer simulation.  ...  In fact, converting a MATLAB model into a working VHDL code for such FPGA-based prototypes requires a considerable effort.  ...  A real-time testbed typically comprises Radio-Frequency (RF) front-ends, signal generation and signal acquisition hardware boards, FPGA-DSP based baseband boards and other specialized equipment (e.g.,  ... 
doi:10.5772/48706 fatcat:ipmfztmvjnagnmt2aigbu75vsq

The JEM-EUSO Mission

M. Bertaina
2009 Nuclear Physics B - Proceedings Supplements  
FPGA/DSP based computer on board, allowing for an online recognition of the shape of the tracks, and therefore an intelligent trigger: the ability to use a more sophisticated algorithm for the trigger  ...  This will allow for a fast development of the software in parallel to the engineering and flight boards, reducing costs and integration time.  ...  (December 2008) JEM-EUSO Report on the Phase A Study  ... 
doi:10.1016/j.nuclphysbps.2009.03.103 fatcat:dvikfzpcrnh65pjkw6qf4oay6a