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A new area and shape function estimation technique for VLSI layouts

G. Zimmerman
<i title="IEEE"> 25th ACM/IEEE, Design Automation Conference.Proceedings 1988. </i> &nbsp;
Placement and shapes can only be optimized if the areas of the modules as a function of the shapes (shape function) can be estimated.  ...  This paper describes a new model for the prediction of shape functions for aspect ratios up to 15. The model is based on the shape and connectivity of adjacent cells.  ...  Placement and shapes can only be optimized if the areas of the modules as a function of the shapes (shape function) can be estimated.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dac.1988.14735">doi:10.1109/dac.1988.14735</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/xpzhbjr7p5einfwta6r52od2py">fatcat:xpzhbjr7p5einfwta6r52od2py</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170830091114/https://www.computer.org/csdl/proceedings/dac/1988/0864/00/00014735.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/b9/4d/b94d386e71233d81c13c73685556ffe477441c0a.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dac.1988.14735"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Optimized Routing Methods for VLSI Placement Design

Mr. Rachapudi Prabhakar
<span title="">2012</span> <i title="IOSR Journals"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/7ftgkqdzrnfspfyjn3usmdd66q" style="color: black;">IOSR Journal of VLSI and Signal processing</a> </i> &nbsp;
For this purpose A new routing method is used -called , A Deep sub-wavelength lithography, (using the 193nm lithography to print 45nm, 32nm, and possibly 22nm integrated circuits), is one of the most fundamental  ...  limitations for the continuous VLSI scaling,.  ...  It shall be noted that LFR is still a relatively new topic, and many techniques are evolving.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.9790/4200-0132731">doi:10.9790/4200-0132731</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/nki45hfgmzeqvd4cxc7keyowwe">fatcat:nki45hfgmzeqvd4cxc7keyowwe</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180602094432/http://www.iosrjournals.org/iosr-jvlsi/papers/vol1-issue3/D0132731.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/c6/ea/c6ea4fbaaaa3d0bba53e8d1e363938600df434ef.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.9790/4200-0132731"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Hybrid genetic algorithms for constrained placement problems

V. Schnecke, O. Vornberger
<span title="">1997</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/dqtjwgdgmjazlimlppwouyrzcq" style="color: black;">IEEE Transactions on Evolutionary Computation</a> </i> &nbsp;
Empirical results are presented for two constrained placement problems, the facility layout problem and the generation of very large scale integrated (VLSI) macro-cell layouts.  ...  Genetic algorithms have proven to be a well-suited technique for solving selected combinatorial optimization problems.  ...  Kuhn for their critical review of the manuscript and the editor and the anonymous reviewers for valuable comments.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/4235.687887">doi:10.1109/4235.687887</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/kznp6vpxojh5habxenirj7i24q">fatcat:kznp6vpxojh5habxenirj7i24q</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170809015916/https://www.inf.utfsm.cl/~mcriff/IA-avanzada/lista-papers/Schnecke.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/49/07/490776ef368fa39de453e07c79a70a8a83d60c6b.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/4235.687887"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Three-phase chip planning-an improved top-down chip planning strategy

Schurmann, Altmeyer, Zimmermann
<span title="">1992</span> <i title="IEEE Comput. Soc. Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ffbycmiwjfgqbewnyare6s37ru" style="color: black;">IEEE/ACM International Conference on Computer-Aided Design</a> </i> &nbsp;
The most important precondition for top-down chip planning is a good area estimation.  ...  However, each estimation has tolerances which result in differences of the estimated shapes in thejloorplan and the final layouts.  ...  The estimated area is available before any floorplan or even a layout is computed. For each cell under design (CUD) we compute a shape function by using the shape functions of its subcells.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/iccad.1992.279306">doi:10.1109/iccad.1992.279306</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/iccad/SchurmannAZ92.html">dblp:conf/iccad/SchurmannAZ92</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/v2jn75jujbcttjmai53q42l3ly">fatcat:v2jn75jujbcttjmai53q42l3ly</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170808194355/http://es.cs.uni-kl.de/publications/datarsg/ScAZ92.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/06/bc/06bc4af1837aaf08857cc69305bc66d8c7372856.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/iccad.1992.279306"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

VLSI Structures for Viterbi Receivers: Part II--Encoded MSK Modulation

P. Gulak, E. Shwedyk
<span title="">1986</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/onirm7ye2bfobnpwuwaopap5yu" style="color: black;">IEEE Journal on Selected Areas in Communications</a> </i> &nbsp;
Ahstrurt -As a specific application of the material presented in Part I, this companion paper identifies VLSI layout strategies for realizing correlative encoded MSK-type Viterbi receivers.  ...  Second-order encoding polynomials give rise to a new type of aiea-efficient VLSI structure which is a generalization of the CCC structure.  ...  , local communication paths, regular control and timing structures, extensibility and minimum die area (yield is an inverse exponential function of die area).  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/jsac.1986.1146300">doi:10.1109/jsac.1986.1146300</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/rvvcpn6lvrarfhiyzmv5r6hfpi">fatcat:rvvcpn6lvrarfhiyzmv5r6hfpi</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20100725222727/http://www.eecg.toronto.edu/~gulak/papers/Gulak86b.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/63/46/63460d97123b95febf2baee7782fbdbd1276ec25.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/jsac.1986.1146300"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Improved Harmony Search Algorithm for Nonslicing Floor Planning of VLSI Chip with Fixed-Outline Constraint
ENGLISH

K.Raveendra, A V Kiranmai
<span title="2012-10-20">2012</span> <i title="Ess &amp; Ess Research Publications"> International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering </i> &nbsp;
It is used to estimate the chip area and wire length prior to the real placement of digital blocks and their interconnections.  ...  VLSI floor planning is an optimization problem; many optimization techniques were adopted in the literature.  ...  A new heuristic method was proposed that applied hybrid simulated annealing (HSA) to represent a nonslicing floorplan with an objective function by restricting the area and wirelength [9] .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.15662/ijareeie.2012.0104018">doi:10.15662/ijareeie.2012.0104018</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/z4gfg66735ck3oohettjaaawtq">fatcat:z4gfg66735ck3oohettjaaawtq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20181221172920/http://www.ijareeie.com:80/upload/october/18_2012_ece_7_EEIE%20ISS%204.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e4/0d/e40d87adc1725a3c500d9baec4d99d774c04d588.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.15662/ijareeie.2012.0104018"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Yield Analysis and Optimization [chapter]

Puneet Gupta, Evanthia Papadopoulou
<span title="2008-11-12">2008</span> <i title="Auerbach Publications"> Handbook of Algorithms for Physical Design Automation </i> &nbsp;
Estimated typical cost of modern 300mm or 12inch wafer 0.13 µm process fabrication plant is $2-4 billion. Typical number of processing steps for a modern integrated circuit is more than 150.  ...  In this chapter, we are going to discuss yield loss mechanisms, yield analysis and common physical design methods to improve yield.  ...  Stratified sampling can increase the accuracy of the prediction by dividing the layout area into a number of regions (strata) for which critical area is estimated using sampling techniques.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1201/9781420013481.ch37">doi:10.1201/9781420013481.ch37</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/klivuybh6ncdxelz3frofmleum">fatcat:klivuybh6ncdxelz3frofmleum</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20110401115949/http://www.inf.usi.ch/faculty/papadopoulou/publications/bookchapter08.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/14/2a/142aaacafc6b3f7adc52c158789db41c0b9324fc.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1201/9781420013481.ch37"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Methods for Hierarchical Automatic Layout of Custom LSI Circuit Masks

B.T. Preas, C.W. Gwyn
<span title="">1978</span> <i title="IEEE"> 15th Design Automation Conference </i> &nbsp;
A new automatic IC mask layout code is described which avoids most of the problems inherent in the present generation of layout codes such as lack of flexibility~ inefficient use of area, and restricted  ...  The structured hierarchical layout approach, construction graphs, and placement and routing algorithms are outlined.  ...  M. vanCleemput of Stanford University for their helpful discussions and suggestions concerning the architecture and development of a general IC layout code and guidance during the initial phases of the  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dac.1978.1585171">doi:10.1109/dac.1978.1585171</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ddgogovqurbz3ogfnwtgst6tkq">fatcat:ddgogovqurbz3ogfnwtgst6tkq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170706121706/https://www.cs.york.ac.uk/rts/docs/DAC-1964-2006/PAPERS/1978/DAC78_206.PDF" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/6f/d9/6fd97482f38bf0d4e1dece7dec99c5cd551d19b7.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dac.1978.1585171"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Optimization of Thermal Aware VLSI Non-Slicing Floorplanning Using Hybrid Particle Swarm Optimization Algorithm-Harmony Search Algorithm

Sivaranjani Paramasivam, Senthilkumar Athappan, Eswari Devi Natrajan, Maheswaran Shanmugam
<span title="">2016</span> <i title="Scientific Research Publishing, Inc,"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/7xp3xydesfgwbon56mgufqzvea" style="color: black;">Circuits and Systems</a> </i> &nbsp;
It is the process of estimating the positions and shapes of the modules.  ...  Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips.  ...  Weighted sum technique is used to merge multiobjective function into a scalar objective function.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.4236/cs.2016.75048">doi:10.4236/cs.2016.75048</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/yitpnapd7vbhlcrla627vkt4i4">fatcat:yitpnapd7vbhlcrla627vkt4i4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170923052901/http://file.scirp.org/pdf/CS_2016042913394250.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e3/44/e344ccecb24e8c64ac767a4e0e93c47561b859d6.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.4236/cs.2016.75048"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> Publisher / doi.org </button> </a>

Contrasts in Physical Design between LSI and VLSI

W.R. Heller
<span title="">1981</span> <i title="IEEE"> 18th Design Automation Conference </i> &nbsp;
u e s facilitating rapid, i n t e r a c t i v e a d a p t a t i o n of f u n c t i o n a l logic design to the layout and i n t e r c o n n e c t i o n of "macros" on large chips.  ...  With all this growth, a l t e r n a t i v e s in VLSI design style as well as packaging have to be considered.  ...  Overall, the benefits of shaping the layout a,d tuning the communication of functional units sharing a custom FET chip come from three sources: (a| even if each functional box is built b~ regular repetition  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dac.1981.1585426">doi:10.1109/dac.1981.1585426</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/7wu2j5ur3ncizenzbjekbibvz4">fatcat:7wu2j5ur3ncizenzbjekbibvz4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170706121855/https://www.cs.york.ac.uk/rts/docs/DAC-1964-2006/PAPERS/1981/DAC81_676.PDF" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/7e/b6/7eb6c432581b6516c29a1e9b88cac457fafb1013.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dac.1981.1585426"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

An Efficient Data Structure Layout Design for Spatial Data Organization in Geographic Information System

Animesh Tripathy, Prashanta Kumar Patra
<span title="2010-10-10">2010</span> <i title="Foundation of Computer Science"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/b637noqf3vhmhjevdfk3h5pdsu" style="color: black;">International Journal of Computer Applications</a> </i> &nbsp;
It is a technique initially used in VLSI layout editing systems. GIS systems store spatial data using rectangular objects.  ...  This paper presents a design for map reading based on Corner Stitching for handling the spatial data. Corner Stitching is a technique for representing the rectangular two dimensional objects.  ...  It is a technique initially used in VLSI layout editing systems.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5120/1276-1602">doi:10.5120/1276-1602</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/5qsfyzyoqjbrpimukpcwjdprt4">fatcat:5qsfyzyoqjbrpimukpcwjdprt4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170809195859/http://www.ijcaonline.org/volume7/number9/pxc3871602.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/02/35/0235c715e7a2248d8219f8cb3cf9a04fbe5cecda.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5120/1276-1602"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Performance evaluation of heuristic algorithms in floor planning for ASIC design

S. Nazeer Hussain, K Hari Kishore
<span title="2017-12-31">2017</span> <i title="Science Publishing Corporation"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/piy2nrvrjrfcfoz5nmre6zwa4i" style="color: black;">International Journal of Engineering &amp; Technology</a> </i> &nbsp;
A study on physical design of VLSI Floor planning is discussed using optimization techniques for betterment in performance of VLSI chip.  ...  Different heuristic and meta-heuristic algorithms are proposed and suggested by many researchers for solving the VLSI Floor plan problem.  ...  [6] proposed a technique that concentrates on the reduction of area as an improvised harmony search algorithm and Twin memory Harmony search algorithm for VLSI floor planning.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.14419/ijet.v7i1.5.9122">doi:10.14419/ijet.v7i1.5.9122</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/xuffvmbsn5gk3ab4libtdop4ee">fatcat:xuffvmbsn5gk3ab4libtdop4ee</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180721041357/https://www.sciencepubco.com/index.php/ijet/article/download/9122/3111" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/2e/15/2e15db4bb894fd0f15ad3f6a03b580e5c2480cb6.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.14419/ijet.v7i1.5.9122"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> Publisher / doi.org </button> </a>

Performance Enhancement of Standard Cell Placement Techniques using Memetic Algorithm

Aaquil Bunglowala, B. M. Singhi, Ajay Verma
<span title="2010-12-01">2010</span> <i title="Foundation of Computer Science"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/b637noqf3vhmhjevdfk3h5pdsu" style="color: black;">International Journal of Computer Applications</a> </i> &nbsp;
A comparison of MA with the already established results for SCP using conventional and Hybrid techniques by the author depicts improvement in the performance of SCP algorithm in terms of solution quality  ...  Here, exploitation is the process of visiting entirely new regions of a search space where the gain can also be high.  ...  INTRODUCTION The design of circuit for VLSI is accomplished in several iterative stages including system specifications, functional design, logic design, circuit design and physical design.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5120/1535-138">doi:10.5120/1535-138</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ho4vbd2gq5e45knue6z3vnpnmm">fatcat:ho4vbd2gq5e45knue6z3vnpnmm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170813084206/http://www.ijcaonline.org/ecot/number2/SPE138T.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/54/38/5438f5e49e0d9420f205160997fca6fed7b10cc2.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5120/1535-138"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

VLSI circuit placement with rectilinear modules using three-layer force-directed self-organizing maps

R.-I. Chang, Pei-Yung Hsiao
<span title="">1997</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/22mhkeaq5zdqlmtti5oidj26fi" style="color: black;">IEEE Transactions on Neural Networks</a> </i> &nbsp;
In this paper, a three-layer force-directed selforganizing map is designed to resolve the circuit placement problem with arbitrarily shaped rectilinear modules.  ...  With the collective computing from hidden neurons, these rectilinear modules can correctly interact with each other and finally converge to a good placement result.  ...  ACKNOWLEDGMENT The authors would like to thank the anonymous referees and Y.-L. J. Chiu for their valuable suggestions about this paper.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/72.623207">doi:10.1109/72.623207</a> <a target="_blank" rel="external noopener" href="https://www.ncbi.nlm.nih.gov/pubmed/18255708">pmid:18255708</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/x536a2dehncjxazrb7rjvjzjeu">fatcat:x536a2dehncjxazrb7rjvjzjeu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170814213054/https://ir.nctu.edu.tw/bitstream/11536/320/1/A1997XT98500009.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/7f/f8/7ff8a01a7f0001a515d701e3aa40049183bb0846.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/72.623207"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Accurate layout area and delay modeling for system level design

Ramachandran, Kurdahi, Gajski, Wu, Chaiyakul
<span title="">1992</span> <i title="IEEE Comput. Soc. Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ffbycmiwjfgqbewnyare6s37ru" style="color: black;">IEEE/ACM International Conference on Computer-Aided Design</a> </i> &nbsp;
In order to establish a more realistic assessment of layout effects, we proposed a new layout model which accurately and efficiently accounts for the effects of wiring and Poorplanning on the area and  ...  Specifreally, we are interested in predicting the layout area and delay of a given structural RT level design.  ...  Acknowledgements The authors would like to acknowledge the students in the VLSI design classes at UCI who provided the layouts used for benchmarking our model.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/iccad.1992.279347">doi:10.1109/iccad.1992.279347</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/iccad/RamachandranKGWC92.html">dblp:conf/iccad/RamachandranKGWC92</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/6hnr5z74mrckrg4ggcaq4437ey">fatcat:6hnr5z74mrckrg4ggcaq4437ey</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20190223025414/http://pdfs.semanticscholar.org/40b7/8a44d0ddbe2ebe30d55698c040fedae7c66c.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/40/b7/40b78a44d0ddbe2ebe30d55698c040fedae7c66c.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/iccad.1992.279347"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>
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