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Testing SoC Interconnects for Signal Integrity Using Extended JTAG Architecture

M.H. Tehranipour, N. Ahmed, M. Nourani
2004 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This architecture includes: 1) a modified driving cell that generates patterns according to multiple transitions fault model and 2) an observation cell that monitors signal integrity violations.  ...  To fully comply with the conventional Joint Test Action Group Standard, two new instructions are used to control cells and scan activities in the integrity test mode.  ...  ACKNOWLEDGMENT The authors would like to thank the authors of [5], Prof. J. Cong, J. Fang, and Y. Zhang, for providing the benchmark circuits. Special thanks go to Y.  ... 
doi:10.1109/tcad.2004.826540 fatcat:glqj2n4vsbfs5borbg4xvlgyve

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs [chapter]

Mehrdad Nourani, Amir Attarha, Krishnendu Chakrabarty
2002 SOC (System-on-a-Chip) Testing for Plug and Play Test Automation  
In this paper, we first define a model for integrity faults on the high-speed interconnects.  ...  Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips.  ...  Acknowledgement The authors thank Nagaraj NS (Texas Instruments, Inc.) and Jerry Tallinger (OEA International, Inc.) for providing their simulator packages and helpful comments.  ... 
doi:10.1007/978-1-4757-6527-4_12 fatcat:cxgzdzhu3becxlez7t2kjuvfwe

Multilevel Full-Chip Routing With Testability and Yield Enhancement

Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We propose a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement.  ...  We augment the traditional multilevel framework of coarsening and uncoarsening by introducing a preprocessing stage that analyzes the interconnect structure for better resource estimation before the coarsening  ...  Signal integrity is also an important factor that affects yield in nanometer IC technology [1] , and the crosstalk fault is a major source that contributes to the loss of signal integrity in nanometer  ... 
doi:10.1109/tcad.2007.895587 fatcat:t4des4udfjgxfnvb7kcumnktei

Embedded software-based self-test for programmable core-based designs

A. Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, L. Chen, S. Dey
2002 IEEE Design & Test of Computers  
Thus, externally testing SoCs translates into increasing yield loss, because guardbanding to cover tester errors results in the loss of increasingly more good chips.  ...  WITH THE GROWING popularity of system-ona-chip (SoC) architectures, demands for short time to market and rich functionality have driven design houses to adopt a new core-based SoC design flow.  ...  Chen and colleagues concentrate on testing the data and address bus in a processor-based SoC. 6 Their approach uses the maximum aggressor (MA) fault model to model crosstalk effects on the interconnects  ... 
doi:10.1109/mdt.2002.1018130 fatcat:fyyiaiaoj5dvzf6otfkzjqx25m

Program Schedule - October 8, 2019 (Hotel Metropolitan Sendai)

2019 2019 International 3D Systems Integration Conference (3DIC)  
The guard ring enhances the insertion loss by up to 1.6 dB and the crosstalk isolation by 20 -26 dB across a range of 0 -40 GHz.  ...  The proposed noise reduction technique features low power and a small area and could be a novel solution for the deep neural networks (DNN) chip using analog signal processing method.  ...  The measurement results for an experimental chip show the effectiveness of our new design.  ... 
doi:10.1109/3dic48104.2019.9058792 fatcat:6kz54ru5uzdbzeecpentkxprqe

Testing On-Die Process Variation in Nanometer VLSI

Mehrdad Nourani, Arun Radhakrishnan
2006 IEEE Design & Test of Computers  
A challenge common to process engineers and circuit designers in trying to meet this demand is the effect of process variation (PV) on design characteristics such as functionality and performance.  ...  Our PV test methodology includes defining the PV fault model; deciding on types, numbers, and positions of a small distributed network of frequency-sensitive sensors (ROs); and designing an efficient,  ...  Acknowledgments This work was supported in part by National Science Foundation Career Award CCR-0130513.  ... 
doi:10.1109/mdt.2006.157 fatcat:xofobxfjlndyngizqnian4x3d4

A roadmap and vision for physical design

Andrew B. Kahng
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
. (5) The scope of physical design must expand (up to package and system, down to manufacturing interfaces, out to novel implementation technologies, etc.), even as renewed focus is placed on basic optimization  ...  back-filling and formulation over innovation and optimization. (4) The physical design field must become more mature and efficient in how it prioritizes research directions and uses its human resources  ...  Examples include analog layout synthesis and reuse; layout-BIST synergies for "deep-submicron fault models"; new paradigms for global signaling, synchronization and system-level interconnect; modeling  ... 
doi:10.1145/505388.505416 dblp:conf/ispd/Kahng02 fatcat:6xefj4rzmbhkrab7uskhi6s2ya

A roadmap and vision for physical design

Andrew B. Kahng
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
. (5) The scope of physical design must expand (up to package and system, down to manufacturing interfaces, out to novel implementation technologies, etc.), even as renewed focus is placed on basic optimization  ...  back-filling and formulation over innovation and optimization. (4) The physical design field must become more mature and efficient in how it prioritizes research directions and uses its human resources  ...  Examples include analog layout synthesis and reuse; layout-BIST synergies for "deep-submicron fault models"; new paradigms for global signaling, synchronization and system-level interconnect; modeling  ... 
doi:10.1145/505415.505416 fatcat:qphnbldeyzcpbhl2bpqyuzdwsa

Testing embedded-core-based system chips

Y. Zorian, E.J. Marinissen, S. Dey
1999 Computer  
This core-based design poses a series of new challenges, especially in the domains of manufacturing test and design validation and debug.  ...  Advances in semiconductor process and design technology enable the design of complex system chips.  ...  We thank Robert Arendsen and Maurice Lousberg of Philips for providing us with useful feedback on draft versions of this paper.  ... 
doi:10.1109/2.769444 fatcat:vd7nx4xhwvglnfiqnu7fpiczku

Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation

Ravishankar Arunachalam, Ronald DeShawn Blanton, Lawrence T. Pileggi
2002 VLSI design (Print)  
Neighboring line switching can contribute to a large portion of the delay of a line for today's deep submicron designs.  ...  The impact of this switching on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded.  ...  INTRODUCTION Analyzing the impact of crosstalk on delay is critical for present day deep submicron circuits.  ... 
doi:10.1080/1065514021000012228 fatcat:v5yneyqzfjbclokwi4bvy5ngvm

Infrastructure for Detector Research and Development towards the International Linear Collider [article]

J. Aguilar, P. Ambalathankandy, T. Fiutowski, M. Idzik, Sz. Kulis, D. Przyborowski, K. Swientek, A. Bamberger, M. Köhli, M. Lupberger, U. Renz, M. Schumacher, Andreas Zwerger (+256 others)
2012 arXiv   pre-print
The EUDET-project was launched to create an infrastructure for developing and testing new and advanced detector technologies to be used at a future linear collider.  ...  The aim was to make possible experimentation and analysis of data for institutes, which otherwise could not be realized due to lack of resources.  ...  Acknowledgement This work is supported by the Commission of the European Communities under the 6th Framework Programme "Structuring the European Research Area", contract number RII3-026126.  ... 
arXiv:1201.4657v1 fatcat:6gmm6jlirrhq3ar6tggd5ht6yq

Testing SoC interconnects for signal integrity using boundary scan

M.H. Tehranipour, N. Ahmed, M. Nourani
Proceedings. 21st VLSI Test Symposium, 2003.  
As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-on-chips is becoming dominant  ...  More specifically, distortion (integrity loss) of signals traveling on high-speed interconnects can no longer be ignored.  ...  ACKNOWLEDGEMENTS This work was supported in part by the National Science Foundation CAREER Award #CCR-0130513.  ... 
doi:10.1109/vtest.2003.1197647 dblp:conf/vts/TehranipourAN03 fatcat:dgz23ovchfhbpigb43bm3koqua

A design methodology for 2D sparse NDE arrays using an efficient implementation of refracted-ray TFM

Jerzy Dziewierz, Timothy Lardner, Anthony Gachagan
2013 2013 IEEE International Ultrasonics Symposium (IUS)  
Background, Motivation and Objective Developing new technologies that enable the repair or replacement of diseased or injured tissues and organs is a major focus of tissue engineering.  ...  Recent advances in the field of tissue engineering include the engineering of skin, cartilage, and bladder, all of which are relatively thin tissues that can rely on diffusion for the delivery of oxygen  ...  The authors acknowledge the ANR and DGA for their support under the project Metactif, grant ANR-11-ASTR-015.  ... 
doi:10.1109/ultsym.2013.0035 fatcat:th5znfh7y5bklfdbmhb4u6iq2i

Front Matter: Volume 7314

Proceedings of SPIE, Alex A. Kazemi, Bernard C. Kress
2009 Photonics in the Transportation Industry: Auto to Aerospace II  
Werniki, New York Institute of Technology (United States) 7314 0P Propogation loss with frequency of ultrasound guided waves in a composite metal-honeycomb structure [7314-25] I.  ...  SPIEDigitalLibrary.org Paper Numbering: Proceedings of SPIE follow an e-First publication model, with papers published first online and then in print and on CD-ROM.  ...  Gregory Wilkins and Chris Werniki would like to thank NAVAIR for their support and hospitality while their work was done. ACKNOWLEDGEMENTS We acknowledge the support of the U.S.  ... 
doi:10.1117/12.833099 fatcat:sg4v4pv3uve2bfyovrzzxtqgbe

Energy and wavelength scaling of shock-ignited inertial fusion targets

S Atzeni, A Marocchino, A Schiavi, G Schurtz
2013 New Journal of Physics  
By mapping the ab-intio result into an effective spin model we show that the system has a manifold of almost degenerate ground states.  ...  We disucss how this kind of multiferrolectricity can be manipulated by imputrities and light pulses and show estimates of the effect in CuO.  ...  These results open the way to the emission of heralded single photons and entangled photon pairs from integrated devices [3a,b].  ... 
doi:10.1088/1367-2630/15/4/045004 fatcat:c4lh6z3uavbktgx4didzjqxoiy
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