Filters








16,389 Hits in 3.7 sec

A Synchronization Method for Register Traces of Pipelined Processors [chapter]

Ralf Dreesen, Thorsten Jungeblut, Michael Thies, Mario Porrmann, Uwe Kastens, Ulrich Rückert
2009 IFIP Advances in Information and Communication Technology  
This method considers pipeline hazards and non-uniform write latencies.  ...  To simplify the validation of a processor, we further have implemented an automatic validation environment that includes a tool which points the developer directly to erroneous instructions.  ...  under grant numbers 01BU0661 (MxMobile) and 01BU0643 (Easy-C).  ... 
doi:10.1007/978-3-642-04284-3_19 fatcat:kurzupcbenb3zh5iz5vvuap4ly

Asynchronous Design—Part 2: Systems and Methodologies

Steven M. Nowick, Montek Singh
2015 IEEE design & test  
Finally, two sidebars provide a summary of asynchronous processors and architectures, as well as testing.  ...  specification languages and CAD tool flows.  ...  Acknowledgment The authors appreciate the funding support of the National Science Foundation under Grants CCF-1219013, CCF-0964606, and OCI-1127361.  ... 
doi:10.1109/mdat.2015.2413757 fatcat:bpxnljdkofh6ppyovk6sp4pknm

Processor Modeling and Design Tools [chapter]

Prabhat Mishra, Nikil Dutt
2006 Industrial Information Technology  
Time-to-market pressure coupled with short-product lifetimes create a critical need for design automation in processor development.  ...  The processor is modeled using a specification language such as Architecture Description Language (ADL).  ...  These cores are bound to a single processor template whose architecture and tools can be modified to a certain degree. The second approach is based on processor specification languages.  ... 
doi:10.1201/9781420007947.ch8 fatcat:azirpu6yajf2dkvpiiqhecdise

Retargetable generation of TLM bus interfaces for MP-SoC platforms

Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel
2005 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '05  
The generated processor cores, adaptors and bus nodes are applied in the exemplary design of a JPEG decoding platform.  ...  In order to meet flexibility, performance and energy efficiency constraints, future SoC (System-on-Chip) designs will contain an increasing number of heterogeneous processor cores combined with a complex  ...  Designing these platforms requires a systematic methodology and suitable tooling for obtaining optimal results in a reasonable design time.  ... 
doi:10.1145/1084834.1084898 dblp:conf/codes/WieferinkLAMMNK05 fatcat:rjf6273bfbh7djndwp3baw5pke

Performance Evaluation of Nonlinear Pipeline through UML

Vipin Saxena, Manish Shrivastava
2010 International Journal of Computer and Electrical Engineering  
To demonstrate the performance, a well known Unified Modeling Language (UML) is used for modeling of floating-point nonlinear pipeline.  ...  Pipelining is an architectural approach for speeding up the floating-point arithmetic operations.  ...  Hanumaiah, Vice-Chancellor, Babasaheb Bhimrao Ambedkar University (A Central University), Vidya Vihar, Rae Bareilly Road, Lucknow, India, for providing excellent computation facilities in the University  ... 
doi:10.7763/ijcee.2010.v2.241 fatcat:zbaoya347fh57l57o7osrdazdy

NoGapCL: A flexible common language for processor hardware description

Wenbiao Zhou, Per Karlstrom, Dake Liu
2010 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems  
NoGap (Novel Generator of Micro Architecture and Processor) is a tool for ASIP designs, utilizing hardware multiplexed data paths.  ...  One of the main advantages of NoGap compared to other EDA tools for processor design, is that NoGap impose few limits on the architecture and thus design freedom.  ...  Current ADL tools for processor design assumes a lot about the underlying architecture of the processor and thus limit the design freedom for novel processor architectures.  ... 
doi:10.1109/ddecs.2010.5491778 dblp:conf/ddecs/ZhouKL10 fatcat:dxhj37k43vg5hhq2twafvr776a

Design Space Exploration of Partially Re-configurable Embedded Processors

A. Chattopadhyay, W. Ahmed, K. Karuri, D. Kammler, R. Leupers, G. Ascheid, H. Meyr
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
Consequently, a new design approach with partial re-configurability on the application-specific processor is attracting strong research interest.  ...  To address this issue, in this paper, a high-level specification for reconfigurable processors is proposed.  ...  To allow a generic design space exploration for the complete rASIP in a single framework, an interesting approach is adopted by [9] . Here, the base processor is modelled using an ADL.  ... 
doi:10.1109/date.2007.364611 dblp:conf/date/ChattopadhyayAKKLAM07 fatcat:g42vjdaqsvcnlffa6tsddcypya

Automatic Low Power Optimizations during ADL-driven ASIP Design

A. Chattopadhyay, D. Kammler, E. Witte, O. Schliebusch, H. Ishebabi, B. Geukes, R. Leupers, G. Ascheid, H. Meyr
2006 2006 International Symposium on VLSI Design, Automation and Test  
ern pipelined embedded processors.  ...  Architecture Description Languages (ADLs) offer the ASIP design-With increasing design complexity, automatic clock gating tools ers a quick and optimal design convergence by automatically gener-are getting  ...  An improved and pins as well as coding elements can be accessed in the same way In LISA, an operation is the central element to describe the tim-Pipeline Controller ing and the behavior of a processor  ... 
doi:10.1109/vdat.2006.258140 fatcat:ntckq22pnraqdpekaxsieat7ey

A proposed synthesis method for Application-Specific Instruction Set Processors

Péter Horváth, Gábor Hosszú, Ferenc Kovács
2015 Microelectronics Journal  
Contrary to this, the final register-transfer level models are usually created, at least partly, manually. This paper presents a novel approach for automated hardware model generation for ASIPs.  ...  The new solution is based on a novel abstract ASIP model and a modeling language (Algorithmic Microarchitecture Description Language, AMDL) optimized for this architecture model.  ...  Acknowledgment The work reported in the paper has been developed in the framework of the project "Talent care and cultivation in the scientific workshops of BME".  ... 
doi:10.1016/j.mejo.2015.01.001 fatcat:6gu6fd2stnbpvcpfugaku3cnje

FPGA prototyping of a RISC processor core for embedded applications

M. Gschwind, V. Salapura, D. Maurer
2001 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
now make hardware emulation practical and cost effective for embedded processor designs.  ...  In this work, we describe the use of a reconfigurable processor core based on an RISC architecture as starting point for application-specific processor design.  ...  Mautner for his help with the final partitioning and placement. The Synopsys and Xilinx XACT tools have been made available to them through the EUROPRACTICE program of the European Commission.  ... 
doi:10.1109/92.924027 fatcat:y2lgnrazwbfchixzfge7kpmbxu

Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

Martin Schoeberl, Pascal Schleuniger, Wolfgang Puffitsch, Florian Brandner, Christian W. Probst, Marc Herbstritt
2011 Design, Automation, and Test in Europe  
The compiler also plays a central role in optimizing the application for the WCET instead of average case performance.  ...  In this paper we present Patmos, a processor optimized for low WCET bounds rather than high average case performance. Patmos is a dual-issue, statically scheduled RISC processor.  ...  A disciplined approach for the design of true WCET-aware optimizations is, however, not known and still considered an open problem.  ... 
doi:10.4230/oasics.ppes.2011.11 dblp:conf/date/SchoeberlSPBP11 fatcat:f3mbwaezuvbeppzfkclo426g2q

Reconfigurable Multiprocessor Systems: A Review

Taho Dorta, Jaime Jiménez, José Luis Martín, Unai Bidarte, Armando Astarloa
2010 International Journal of Reconfigurable Computing  
A number of state-of-the-art systems published in this field are presented and classified. Design methods and challenges are also discussed.  ...  Modern digital systems demand increasing electronic resources, so the multiprocessor platforms are a suitable solution for them.  ...  Acknowledgments This work has been supported by the Department of Education, Universities and Research of the Basque Government within the fund for research groups of the Basque university system IT394  ... 
doi:10.1155/2010/570279 fatcat:uho74omrjzbjhe5nwm36zupxam

Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors

Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro Lopez
2007 19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'07)  
The permanent need of evaluating new designs on each of these components motivates the development of tools which simulate the system working as a whole.  ...  A set of simulation examples is also included for illustrative purposes.  ...  Acknowledgements This work was supported by CICYT under Grant TIN2006-15516-C04-01, by Consolider-Ingenio 2010 under Grant CSD2006-00046 and by the Generalitat Valenciana under grant GV06/326.  ... 
doi:10.1109/sbac-pad.2007.17 fatcat:litbjuzotnh2bo3s5hjgjbtoce

Recent Developments in Configurable and Extensible Processors

Grant Martin
2006 IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)  
It also discusses some of our future evolution -in particular, the move from a single processor focus to a multi-processor SoC (MPSoC) focus.  ...  There have been some interesting technology developments in the area of configurable and extensible processors in the last few years.  ...  Single processor designs could often be done with relatively rudimentary system level design tools. However, multiprocessor SoC is beginning to require much more complex ESL tools and models [10] .  ... 
doi:10.1109/asap.2006.57 dblp:conf/asap/Martin06 fatcat:xymdcs3kyrd7bcnb5h56wc3h5u

Instruction-Based Energy Estimation Methodology for Asymmetric Manycore Processor Simulations

William Song, Sudhakar Yalamanchili, Saibal Mukhopadhyay, Arun Rodrigues
2012 Proceedings of the Fifth International Conference on Simulation Tools and Techniques  
Processor power is a complex function of device, packaging, microarchitecture, and application.  ...  an average simulation time speedup of 74X for a 16-core asymmetric x86 ISA processor model with multiple clock domains operating at different frequencies.  ...  ACKNOWLEDGEMENTS The authors gratefully acknowledge the support of this work by the Semiconductor Research Corporation (Task ID# 2084.001), National Science Foundation under grant NSF CNS-855110, and Sandia  ... 
doi:10.4108/icst.simutools.2012.247770 dblp:conf/simutools/SongYRM12 fatcat:voe26wagbzedtozsb2e74lvtfq
« Previous Showing results 1 — 15 out of 16,389 results