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Hardware/Software Partitioning and Static Task Scheduling on Runtime Reconfigurable FPGAs using a SMT Solver

Mingxuan Yuan, Xiuqiang He, Zonghua Gu
2008 2008 IEEE Real-Time and Embedded Technology and Applications Symposium  
schedule length, in the framework of Satisfiability Modulo Theories (SMT) with Linear Integer Arithmetic.  ...  FPGAs are often used together with a CPU as hardware accelerators.  ...  Each task has both a HW implementation that can run on the FPGA, and a SW implementation that can run on the CPU. Communication between the FPGA and CPU incurs a fairly large delay.  ... 
doi:10.1109/rtas.2008.39 dblp:conf/rtas/YuanHG08 fatcat:tyzjgol3szhvjhuy6molkmex7i

Hardware/software partitioning and pipelined scheduling on runtime reconfigurable FPGAs

Mingxuan Yuan, Zonghua Gu, Xiuqiang He, Xue Liu, Lei Jiang
2010 ACM Transactions on Design Automation of Electronic Systems  
Given an application in the form of a task graph with known execution times on the HW (FPGA) and SW (CPU), and known area sizes on the FPGA, find an valid allocation of tasks to either HW or SW and a static  ...  Given an input task graph, construct a pipelined schedule on a PRTR FPGA with the goal of maximizing system throughput while meeting a given end-to-end deadline. Both problems are NP-hard.  ...  This article is structured as follows: we present the SMT model for HW/SW partitioning on a hybrid CPU/FPGA device in Section 2; the SMT model and a heuristic algorithm based on kernel recognition for  ... 
doi:10.1145/1698759.1698763 fatcat:xnur36bxt5hhja2uh7v5hjqnaq

A Prototype Multithreaded Associative SIMD Processor

Kevin Schaffer, Robert A. Walker
2007 2007 IEEE International Parallel and Distributed Processing Symposium  
In this paper, we describe a SIMD processor architecture that combines a fully pipelined broadcast/reduction network with hardware multithreading to reduce performance degradation as the number of processors  ...  This is especially true of hybrid SIMD models, such as associative computing, that make extensive use of global search operations.  ...  ASC Processor Prototypes Several students at Kent State have developed a prototype ASC Processor that implements the associative computing model.  ... 
doi:10.1109/ipdps.2007.370471 dblp:conf/ipps/SchafferW07 fatcat:4jpenxo2cfffrb5t4wk4aikc6i

Architectures and compilers

B. Di Martino
2003 Eleventh Euromicro Conference on Parallel, Distributed and Network-Based Processing, 2003. Proceedings.  
They range from two-four processor configurations typical of desktop systems, to large servers moving to one hundred processors.  ...  Hierarchical distributed-shared memory multiprocessor architectures are emerging as a flexible architectural model: it combines the two paradigms of shared and distributed address space in one system,  ... 
doi:10.1109/empdp.2003.1183563 fatcat:x64qlonny5ebjk5llzpheonth4

Chip-Size Evaluation of a Multithreaded Processor Enhanced with a PID Controller [chapter]

Michael Bauer, Mathias Pacher, Uwe Brinkschulte
2010 Lecture Notes in Computer Science  
The overhead introduced by the PID controller implementation in the VHDL model of an embedded Java real-time-system is examined.  ...  In this paper the additional chip size of a Proportional/Integral/Differential (PID) controller in a multithreaded processor is evaluated.  ...  Use of a controller to stabilize the throughput to the size of the microprocessor to estimate the practicability of the use of such a controller in a FPGA or even an ASIC implementation; this work is described  ... 
doi:10.1007/978-3-642-16256-5_3 fatcat:yvcomouhibat5gdyxfitelchoi

Guest Editorial

Milos Manic, Luís Gomes, Aleksander Malinowski
2011 IEEE transactions on industrial electronics (1982. Print)  
Gaussian-mixture models on a parallel FPGA platform with a double-buffering-scheme-modeled likelihood of observing an acoustic-feature vector.  ...  Embedded processors and hardware accelerators were explored in the manuscript entitled "The ARPA-MT Embedded SMT Processor and Its RTOS Hardware Accelerator" by Oliveira et al.  ... 
doi:10.1109/tie.2010.2098638 fatcat:f3kb2nhperdybhrrfntvepdmwe

A Multithreaded Soft Processor for SoPC Area Reduction

Blair Fort, Davor Capalija, Zvonko Vranesic, Stephen Brown
2006 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines  
The growth in size and performance of Field Programmable Gate Arrays (FPGAs) has compelled System-on-a-Programmable-Chip (SoPC) designers to use soft processors for controlling systems with large numbers  ...  In the case of CIs, the FPGA logic blocks that implement the CIs may have to be replicated for each processor.  ...  The authors observe that workloads comprising a sufficient level of parallelism result in better performance on the SMT processor for the given processor resources.  ... 
doi:10.1109/fccm.2006.10 dblp:conf/fccm/FortCVB06 fatcat:ucepgze7qvfwfkk5c2a2dmv7su

A Lightweight Isolation Mechanism for Secure Branch Predictors [article]

Lutan Zhao, Peinan Li, Rui Hou, Michael C. Huang, Jiazhen Li, Lixin Zhang, Xuehai Qian, Dan Meng
2020 arXiv   pre-print
Our analyses using an FPGA-based RISC-V processor prototype and additional auxiliary simulations suggest that the proposed mechanisms incur a very small performance cost while providing strong protection  ...  We propose a randomized index mechanism of the branch predictor (Noisy-XOR-BP).  ...  For single-threaded core, we implemented the above isolation mechanisms on an FPGA prototyping system of a RISC-V out-of-order processor for a realistic evaluation of the performance impact.  ... 
arXiv:2005.08183v2 fatcat:su6qfgvx7bbqdgcsdcwdhruzem

C-slow Technique vs Multiprocessor in designing Low Area Customized Instruction set Processor for Embedded Applications [article]

Muhammad Adeel Akram, Aamir Khan, Muhammad Masood Sarfaraz
2012 arXiv   pre-print
set extensible processor architecture and others require more number of processing units on a single chip like Thread Level Parallelism (TLP) that includes Simultaneous Multithreading (SMT), Chip Multithreading  ...  A lot of research has been evolved to enhance the performance of embedded processors through parallel computing.  ...  We have discussed many techniques to implement the SMT with different proposed models.  ... 
arXiv:1204.1179v1 fatcat:i2v5ls2upbgxhewerxnmjquxty

How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT [chapter]

Jörg Mische, Irakli Guliashvili, Sascha Uhrig, Theo Ungerer
2010 Lecture Notes in Computer Science  
The application of these enhancements is demonstrated by CarCore, a multithreaded embedded processor that implements the Infineon Tricore instruction set.  ...  This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-time applications.  ...  Simplifications for Single-Threaded CarCore As baseline for the SMT enhancement we implemented a cycle-accurate System-C model and a synthesisable VHDL model of a Tricore-compatible processor.  ... 
doi:10.1007/978-3-642-11950-7_2 fatcat:pj2ckj4qqzgaldltgbu5zaluku

SMT-8036 Based Implementation of Secured Software Defined Radio System for Adaptive Modulation Technique [chapter]

Sudhanshu Mehta, Surbhi Sharma, Rajesh Khanna
2011 Communications in Computer and Information Science  
SDR platform is a massively parallel processor in which transmitter and a part of receiver is implemented on DSP processor and demodulator is implemented on FPGA.  ...  In this thesis we have implemented different digital modulation techniques on SMT-8036 kit which has a DSP (TMS320C6416) and FPGA (VIRTEX I and VIRTEX II) processors.  ... 
doi:10.1007/978-3-642-22720-2_20 fatcat:efjaizgqdvdbhppaju5fqtltfi

Formal Verification of Spacecraft Control Programs Using a Metalanguage for State Transformers [article]

Andrey Mokhov, Georgy Lukyanov, Jakob Lechner
2018 arXiv   pre-print
We present a verification approach designed to help spacecraft engineers reduce the effort required for formal verification of low-level control programs executed on custom hardware.  ...  The verification approach is demonstrated on an industrial case study.  ...  Acknowledgements We would like to thank Neil Mitchell, Charles Morisset, Artem Pelenitsyn and Danil Sokolov for their helpful feedback on an earlier version of this paper.  ... 
arXiv:1802.01738v1 fatcat:sybzckmi6ndelaxu3biek37t34

Formal verification of spacecraft control programs (experience report)

Andrey Mokhov, Georgy Lukyanov, Jakob Lechner
2019 Proceedings of the 12th ACM SIGPLAN International Symposium on Haskell - Haskell 2019  
This experience report presents a verification approach designed to help spacecraft engineers reduce the effort required for formal verification of low-level control programs executed on custom hardware  ...  We present REDFIN, a processing core used in space missions, and its formal semantics expressed using the proposed metalanguage for state transformers, followed by examples of verification of simple control  ...  an earlier version of this paper.  ... 
doi:10.1145/3331545.3342593 dblp:conf/haskell/MokhovLL19 fatcat:7igxehidsrgozfwizncaoizez4

Simultaneous thin-thread processors for low-power embedded systems

Won W. Ro, Jaeyoung Yi, Joon-Sang Park, Joonseok Park
2008 IEICE Electronics Express  
A drawback is that the conventional design of the superscalar processors possesses inherent complexity and power problems which are not easily acceptable in the domain of embedded processors.  ...  However, the upcoming application domain of embedded systems will require more advanced microprocessor cores due to the future computing demands.  ...  The proposed architecture model STT (Simultaneous Thin-Threading) has been developed based on the existing SMT (Simultaneous Multi-Threading) architecture; however, instead of implanting a large issue  ... 
doi:10.1587/elex.5.802 fatcat:axoa4v4bfje63hogzswwg3shci

Susan Eggers Receives Eckert-Mauchly Award for Outstanding Contributions to Computer Architecture

Hank Levy, Susan Eggers
2018 IEEE Micro  
Eggers was one of the leading proponents of SMT as a way to boost parallelism and, with it, performance.  ...  SMT combines hardware multithreading with superscalar processor technology to enable multiple independent threads to issue instructions to multiple functional units in a single cycle.  ...  She was also a member of the team that developed CHiMPS, a C-to-FPGA synthesis compiler that enabled developers to program FPGAs in an imperative language and memory model, while still providing greater  ... 
doi:10.1109/mm.2018.043191127 fatcat:k6infpw5vrahhhv7uomtusuu5e
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