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A new methodology for concurrent technology development and cell library optimization

M. Chew, S. Saxena, T.F. Cobourn, P.K. Mozumder, A.J. Strojwas
1999 Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)  
This paper focuses on our approach for concurrent development of new technologies and optimization of cell libraries for these technologies.  ...  We present a software system called Circuit Surfer which performs this library optimization in a highly automated fashion and with guaranteed correctness in silicon.  ...  Typically, worst case SPICE models are developed once for a technology using a subset of circuits.  ... 
doi:10.1109/icvd.1999.745118 dblp:conf/vlsid/ChewSCMS99 fatcat:gncaatiu5bgzfhwp3hhsa2owqi

On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology

B. P. Harish, Navakanta Bhat, Mahesh B. Patil
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
of a digital circuit.  ...  To extend this methodology for a generic technology library with a variety of library elements, modeling of NAND gate delays by response surface methodology (RSM), in terms of process parameters, is carried  ...  Vinay Kumar, Department of Electrical Engineering, Indian Institute of Technology, Bombay, for the useful discussions regarding the SEQUEL simulator.  ... 
doi:10.1109/tcad.2006.883910 fatcat:2aiqowxs7rc3ldnnq7amvtdfwe

Systematic analysis & optimization of analog/mixed-signal circuits balancing accuracy and design time

Antonio Colaci, Gianluigi Boarin, Andrea Roggero, Lorenzo Civardi, Carlo Roma, Andreas Ripp, Michael Pronath, Gunter Strube
2010 Proceedings of the 23rd symposium on Integrated circuits and system design - SBCCI '10  
We chose a double ring oscillator consisting of a Main PLL and a Dither PLL as example to demonstrate how such systematic methodology can even handle large circuits.  ...  In this paper we will demonstrate the benefits of systematic circuit analysis and optimization applied at different abstraction levels of a typical analog and mixed-signal design to address market requirements  ...  Moreover the consistency among parameter influence, scatter plot and Worst Case analysis results, provides a strong and really powerful methodology to deeply check the main reasons of circuit weakness  ... 
doi:10.1145/1854153.1854165 dblp:conf/sbcci/ColaciBRCRRPS10 fatcat:il3g3y7yfze6poxbnyov2itvta

From blind certainty to informed uncertainty

Kurt Keutzer, Michael Orshansky
2002 Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems - TAU '02  
ABSTRACT The accuracy, computational efficiency, and reliability of static timing analysis have made it the workhorse for verifying the timing of synchronous digital integrated circuits for more than a  ...  We argue that computation of the static timing of a circuit requires a dramatic rethinking in order to continue serving its role as an enabler of high-performance designs.  ...  For more than a decade the industrial workhorse for verifying these two timing properties of synchronous digital integrated circuits has been static-timing analysis (STA).  ... 
doi:10.1145/589411.589419 dblp:conf/tau/KeutzerO02 fatcat:f2vkixmlpnelffghweyqzgfyli

From blind certainty to informed uncertainty

Kurt Keutzer, Michael Orshansky
2002 Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems - TAU '02  
ABSTRACT The accuracy, computational efficiency, and reliability of static timing analysis have made it the workhorse for verifying the timing of synchronous digital integrated circuits for more than a  ...  We argue that computation of the static timing of a circuit requires a dramatic rethinking in order to continue serving its role as an enabler of high-performance designs.  ...  For more than a decade the industrial workhorse for verifying these two timing properties of synchronous digital integrated circuits has been static-timing analysis (STA).  ... 
doi:10.1145/589418.589419 fatcat:abyqt4qbmbad7cvervw4v57sma

On switch factor based analysis of coupled RC interconnects

Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
2000 Proceedings of the 37th conference on Design automation - DAC '00  
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology.  ...  This has implications for almost all signal integrity methodologies, e.g., window-based approaches that iteratively determine worst-case coupling effects.  ...  The analysis of worst case switch factor for computing maximum delay on the victim line (setup time analysis) symmetrically applies to yield a best-case switch factor of -1 (for hold time analysis).  ... 
doi:10.1145/337292.337318 dblp:conf/dac/KahngMS00 fatcat:b6fzxvahfbbubl47x2ppz5tiva

Death, taxes and failing chips

Chandu Visweswariah
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Dealing with variability is an increasingly important aspect of highperformance digital integrated circuit design, and indispensable for first-time-right hardware and cutting-edge performance.  ...  This invited paper discusses the methodology, analysis, synthesis and modeling aspects of this problem.  ...  However, it will have a profound impact on the modeling, analysis, verification, synthesis and methodology of high-performance integrated circuits.  ... 
doi:10.1145/775832.775921 dblp:conf/dac/Visweswariah03 fatcat:dmneezinb5dtngemzqesgrph5e

Death, taxes and failing chips

Chandu Visweswariah
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Dealing with variability is an increasingly important aspect of highperformance digital integrated circuit design, and indispensable for first-time-right hardware and cutting-edge performance.  ...  This invited paper discusses the methodology, analysis, synthesis and modeling aspects of this problem.  ...  However, it will have a profound impact on the modeling, analysis, verification, synthesis and methodology of high-performance integrated circuits.  ... 
doi:10.1145/775919.775921 fatcat:i7wwbis2urehjc62byywgik3ya

TACO

Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi
2000 Proceedings of the 37th conference on Design automation - DAC '00  
This paper introduces TACO, a timing analysis methodology that produces tight bounds on worst-and best-case timing for circuits with dominant coupling capacitance.  ...  The methodology utilizes a coupled Ceff gate model for capturing the provably worst-and bestcase delays as a function of the timing-window inputs to the gates.  ...  Acknowledgments The authors would like to thank Alex Suess and Khalid Rahmat from IBM EDA, Fishkill for their help and support in the implementation of TACO in Einstimer and for providing test-case examples  ... 
doi:10.1145/337292.337415 dblp:conf/dac/ArunachalamRP00 fatcat:es6lgt4pinaq3dkivbtz7b4n6m

Frequency Scaling for High Performance of Low-End Pipelined Processors

Athanasios Tziouvaras, Georgios Dimitriou, Michael Dossis, Georgios Stamoulis
2021 Advances in Science, Technology and Engineering Systems  
In this work we propose a better-than-worst-case (BTWC) methodology which enables the processor pipeline to operate at higher clock frequencies compared to the worst-case design approach.  ...  Nevertheless, the performance increase is up to nine times larger than the power consumption increase for each case.  ...  of the integrated circuit.  ... 
doi:10.25046/aj060288 fatcat:xhv2zhuit5eslgepv3ze6s7vce

Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis

Xiaoxiao Wang, Hassan Salmani, Mohammad Tehranipoor, Jim Plusquellic
2008 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems  
In this paper, we propose a current integration methodology to observe Trojan activity in the circuit and a localized current analysis approach to isolate the Trojan.  ...  This paper addresses a new threat to the security of integrated circuits (ICs).  ...  As shown, the Trojan can be easily detected using the method in presence of worst-case process variations considered for Trojan-free circuit to identify the worst-case charge for genuine ICs.  ... 
doi:10.1109/dft.2008.61 dblp:conf/dft/WangSTP08 fatcat:beoionkftjaiplqye2urpri35e

DATE 2006 Special Session: DFM/DFY Design for Manufacturability and Yield - influence of process variations in digital, analog and mixed-signal circuit design

A. Ripp, M. Buhler, M. Buhler, J. Koehl, J. Bickford, J. Hibbeler, U. Schlichtmann, R. Sommer, M. Pronath, A. Ripp
2006 Proceedings of the Design Automation & Test in Europe Conference  
Three main reasons for missing Worst Case Distances [17] approach.  ...  . integrated circuits for high yield.  ... 
doi:10.1109/date.2006.243763 dblp:conf/date/BuhlerKBHSSPR06 fatcat:pu7a6zbvsjecvledk7up5ns5pm

Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design

Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
2008 9th International Symposium on Quality Electronic Design (isqed 2008)  
A performance degradation of 43.5% is observed when the parasitic extracted circuit was subjected to worst case process variation.  ...  A currentstarved voltage controlled oscillator (VCO) is treated as a case study and to the best of the authors' knowledge, this is the first VCO design that accounts for both parasitic degradation and  ...  Characteristics of the Optimal Circuit Conclusions In this paper, we present a novel parasitic and process variation aware design methodology for optimization of performance for RF circuit components  ... 
doi:10.1109/isqed.2008.4479750 dblp:conf/isqed/GhaiMK08a fatcat:hs3zruvowfaslcpgeyllfqcoxm

Taming pattern and focus variation in VLSI design

Fook-Luen Heng, Puneet Gupta, Kafai Lai, Ronald L. Gordon, Jin-Fuw Lee, Lars W. Liebmann
2004 Design and Process Integration for Microelectronic Manufacturing II  
We demonstrate the systematic ACLV by showing a Bossung plot for a nominal 90nm technology node.  ...  We propose a holistic design flow by integrating the technology development process, design process and the manufacturing process.  ...  the 10 cells, and then time the synthesized and placed circuits for best-case, nominal and worst-case.  ... 
doi:10.1117/12.538271 fatcat:cczspfxbgjaaxazuzcnsaoacky

AN IN-SITU TIMING-ERROR PREDICTION AND PREVENTION TECHNIQUE FOR VARIATION-TOLERANT MAC-UNIT

Jasmer Singh, Saha K, GL Pahuja
2017 International Journal of Advanced Research  
As the worst cases rarely occur, so it is always better for the designers to focus on typical cases, called as typical-case design methodology.  ...  Due to this, the traditional worst-case methodology of design is no more effective as process variations require more design margins.  ...  As the worst cases rarely occur, so it is always better for the designers to focus on typical cases, called as typical-case design methodology.  ... 
doi:10.21474/ijar01/4898 fatcat:gteugvrdjvgxjgchltiow4swee
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