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Parallel Algorithms Development for Programmable Devices with Application from Cryptography

Issam W. Damaj
2007 International journal of parallel programming  
The refinements are inspired by the operators of Communicating Sequential Processes (CSP) and map easily to programs in Handel-C (a hardware description language).  ...  State-of-the-art FPGAs are complex hybrid devices that contain up to several millions of gates.  ...  John Hawkins for their insightful comments on the research which is partly presented in this paper.  ... 
doi:10.1007/s10766-007-0046-1 fatcat:2xpaoudqsrcz7af4zvrxxcrcb4

Parallel algorithms development for programmable logic devices

Issam W. Damaj
2006 Advances in Engineering Software  
We take a step-wise refinement approach to the development of correct reconfigurable hardware circuits from formal specifications.  ...  The off-the-shelf refinements are inspired by the operators of Communicating Sequential Processes (CSP) and map easily to programs in Handel-C (a hardware description language).  ...  The development continues by deriving efficient, parallel implementations described in CSP and realised using Handel-C that can be compiled into hardware on an FPGA.  ... 
doi:10.1016/j.advengsoft.2006.01.009 fatcat:fmlpok2bdnbzzpkpr3u4lakyfy

NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs [article]

Paolo Meloni, Alessandro Capotondi, Gianfranco Deriu, Michele Brian, Francesco Conti, Davide Rossi, Luigi Raffo, Luca Benini
2017 arXiv   pre-print
Thanks to our heterogeneous computing model, our platform improves upon the state-of-the-art, achieving a frame rate of 5.5 fps on the end-to-end execution of VGG-16, and 6.6 fps on ResNet-18.  ...  This work presents NEURAghe, a flexible and efficient hardware/software solution for the acceleration of CNNs on Zynq SoCs.  ...  [34] presented a latency-driven design methodology for mapping CNNs on FPGAs.  ... 
arXiv:1712.00994v1 fatcat:s2e2eaafpbcffnutlzktggcooe

NEURAghe

Paolo Meloni, Alessandro Capotondi, Gianfranco Deriu, Michele Brian, Francesco Conti, Davide Rossi, Luigi Raffo, Luca Benini
2018 ACM Transactions on Reconfigurable Technology and Systems  
Thanks to our heterogeneous computing model, our platform improves upon the state-of-the-art, achieving a frame rate of 5.5 fps on the end-to-end execution of VGG-16, and 6.6 fps on ResNet-18.  ...  This work presents NEURAghe, a flexible and efficient hardware/software solution for the acceleration of CNNs on Zynq SoCs.  ...  [37] presented a latency-driven design methodology for mapping CNNs on FPGAs.  ... 
doi:10.1145/3284357 fatcat:nsc2gkpjdbbghmz6wcbrwqhkla

Dynamic Hardware Development

Stephen Craven, Peter Athanas
2008 International Journal of Reconfigurable Computing  
Applications that leverage the dynamic partial reconfigurability of modern FPGAs are few, owing in large part to the lack of suitable tools and techniques to create them.  ...  This paper discusses the creation of a high-level development environment for reconfigurable designs that leverage an existing high-level synthesis tool to enable the design, simulation, and implementation  ...  Based on the CSP model, Impulse C permits the application developer to describe hardware using a large subset of standard C.  ... 
doi:10.1155/2008/901328 fatcat:3itrrcxyhjaijh2fjkhtsap2jy

A Control System Processor Architecture for Complex LTI Controllers

Roger Goodall, Simon Jones, Rene Cumplido-Parra, Fiona Mitchell, Stephen Bateman
2000 IFAC Proceedings Volumes  
Control System Processor (CSP) implemented using a "programmable ASIC" device.  ...  The paper describes the use of FPGA-type devices for implementing complex, high sample rate, linear time invariant controllers.  ...  The processor is implemented together with the appropriate programme in an Actel ProAsic FPGA which is a flash-programmable device (non-volatile), offering a one-chip solution.  ... 
doi:10.1016/s1474-6670(17)35466-6 fatcat:b3obc2auprhstc3sdlc55243si

Design methodology for construction of asynchronous pipelines with Handel-C

R.P. Self, M. Fleury, A.C. Downton
2003 IEE Proceedings - Software  
applied to dense FPGAs. 2  ...  CSP channels are proposed as a means of developing high-level, asynchronous pipeline architectures over and above existing synchronous logic.  ...  Our development methodology iterates from a sequential implementation through to a (possibly) fully parallel one.  ... 
doi:10.1049/ip-sen:20030206 fatcat:ro5ekwlojfbwvm6fdilo67arr4

Mapping high level algorithms onto massively parallel reconfigurable hardware

I. Damaj, J. Hawkins, A. Abdallah
2003 ACS/IEEE International Conference on Computer Systems and Applications, 2003. Book of Abstracts.  
Handle-C is a programming language based on C and extended by parallelism and communication primitives taken from CSP.  ...  The main focus of this paper is on implementing high level functional algorithms in reconfigurable hardware.  ...  Handel-C relies on the parallel constructs in CSP to model concurrent hardware resources. Accordingly, algorithms described with CSP could be implemented with Handle-C.  ... 
doi:10.1109/aiccsa.2003.1227451 fatcat:kckwvs6ugzdw3oaammihgjrlp4

Design of Field Programmable Gate Array Based Emulators for Motor Control Applications

Taha
2012 American Journal of Applied Sciences  
Approach: This study proposes to apply this technique for the conception and implementation of a Real Time Direct Current Machine (RTDCM) emulator for an embedded control application.  ...  Problem Statement: Field Programmable Gate Array (FPGA) circuits play a significant role in major recent embedded process control designs.  ...  To utilize CoDeveloper, developers have to follow its programming approach which is based on Communication Sequential Processes (CSP).  ... 
doi:10.3844/ajassp.2012.1166.1181 fatcat:kqrecrjepfbn5ccgr7ujr6mv5y

Towards facilities for modeling and synthesis of architectures for resource allocation problem in systems engineering

Stephen Creff, Jérôme Le Noir, Eric Lenormand, Sébastien Madelénat
2020 Proceedings of the 24th ACM Conference on Systems and Software Product Line: Volume A - Volume A  
More specifically, this work reports on the use of the Clafer modeling language and its gateway to the CSP Choco Solver, on an industrial case study of heterogeneous hardware resource allocation (GPP-GPGPU-FPGA  ...  Unfortunately, existing languages and approaches do not incorporate this concern, generally favoring solution analysis over exploring a set of candidate architectures.  ...  This article follows a report on the use of the Clafer modeling language [5] and its gateway to the Choco Solver[8] Constraint Solver Programming (CSP), on an implemented industrial case study of heterogeneous  ... 
doi:10.1145/3382025.3414963 dblp:conf/splc/CreffNLM20 fatcat:tmwmzafabfadlo32ygqytsemha

Adaptively Lossy Image Compression for Onboard Processing

Justin Goodwill, David Wilson, Sebastian Sabogal, Alan D. George, Christopher Wilson
2020 2020 IEEE Aerospace Conference  
This hybrid CNN-JPEG approach shows 23.5% better average peak signal-to-noise ratio (PSNR) and 33.5% better average structural similarity index (SSIM) versus standard JPEG on a dataset collected on the  ...  tune the compression ratio to allow for a tradeoff between v PSNR/SSIM and combined file size over a batch of STP-H5-CSP images.  ...  file size by 29.6% when compared to a static QF=90 over a batch of satellite images collected on STP-H5-CSP.  ... 
doi:10.1109/aero47225.2020.9172536 fatcat:ou6b74ywjnckfjxwgicb7nlx4i

Soc Communication Architecture Modeling

Ziaddin Daie Koozekanani, Mina Zolfy Lighvan
2012 Zenodo  
In this paper some of the mostly used methodologies for modeling and representation of on chip communication are investigated.  ...  Our goal is studying the existing methods to extract the requirements of a general representation scheme for communication architecture synthesis.  ...  CSP CSP(Communicating Sequential Processes) [13] is a classical approach for describing the communication in parallel systems.  ... 
doi:10.5281/zenodo.1077354 fatcat:tinbd7fcejaa5kfiznhvzy3raq

A Verified Protocol to Implement Multi-way Synchronisation and Interleaving in CSP [chapter]

Marcel Vinicius Medeiros Oliveira, Ivan Soares De Medeiros Júnior, Jim Woodcock
2013 Lecture Notes in Computer Science  
In previous work, we presented a tool, csp2hc, that translates a subset of CSP into Handel-C source code, which can itself be converted to produce files to program FPGAs.  ...  This subset restricts parallel composition: multisynchronisation and interleaving on shared channels are not allowed. In this paper, we present an extension to csp2hc that removes these restrictions.  ...  In Section 2, we introduce CSP M , Handel-C, and the previous version of csp2hc. Section 3 describes the approach to implement CSP model of parallelism in Handel-C.  ... 
doi:10.1007/978-3-642-40561-7_4 fatcat:ihyyn7tzprgm3gavw2yidtt5ra

Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing

Zain-ul-Abdin, Bertil Svensson
2009 Microprocessors and microsystems  
systems, the architectures of reconfigurable devices have evolved to coarse-grained compositions of functional units or program controlled processors, which are operated in a coordinated manner to improve  ...  of these on energy related properties and scalability.  ...  Acknowledgements We would like to thank our colleagues (Dr. Veronica Gaspes, Jerker Bengtsson, Andreas Persson, and Prof.  ... 
doi:10.1016/j.micpro.2008.10.003 fatcat:k4c63f4k2zbc5a4mfr3vfwqkfe

Inverse Problems, Constraint Satisfaction, Reversible Logic, Invertible Logic and Grover Quantum Oracles for Practical Problems [chapter]

Marek Perkowski
2020 Lecture Notes in Computer Science  
Moreover, building oracles is the fundamental concept in the new approach to solve CSP proposed here and based on Invertible Logic introduced recently by Supriyo Datta and his team.  ...  For instance, several important problems in CAD and Machine Learning can be solved using only two basic operations on set partitions; P 1 P 2 and P 1 Á P 2 .  ...  methodology to solve optimization and CSP problems based on designing oracles bottom-up from a hierarchy of blocks.  ... 
doi:10.1007/978-3-030-52482-1_1 fatcat:xw3kgmienzhh7mmfi4u3n6h7d4
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