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A Method for Minimizing Clock Skew Fluctuations Caused by Interconnect Process Variations

Susumu KOBAYASHI, Fumihiro MINAMI
2013 IEICE transactions on information and systems  
In this paper, we propose a method for minimizing clock skew fluctuations caused by interconnect process variations.  ...  The proposed method identifies the suitable balance of clock buffer size and wire length in order to minimize the clock skew fluctuations caused by the interconnect process variations.  ...  Conclusions We have proposed a method for minimizing clock skew fluctuations caused by interconnect process variations.  ... 
doi:10.1587/transinf.e96.d.1980 fatcat:yjfutb3qinbb7fadmw6esvtktm

Variation-tolerant and low-power clock network design for 3D ICs

Xin Zhao, Saibal Mukhopadhyay, Sung Kyu Lim
2011 2011 IEEE 61st Electronic Components and Technology Conference (ECTC)  
high skew variation by introducing the uncertainties of TSV electrical parasitics, our study demonstrates that a 3D clock network with multiple TSVs can decrease the random effects by using fewer buffers  ...  This paper studies the random characteristics of throughsilicon-via (TSV)-based 3D clock networks, taking into account both die-to-die and within-die process variations in clock buffers, interconnects,  ...  CCF-0546382 and CCF-0917000, the SRC Interconnect Focus Center (IFC), and Intel Corporation.  ... 
doi:10.1109/ectc.2011.5898792 fatcat:lwicspxutjfnvjusqgdwh7de3u

Variant X-Tree Clock Distribution Network and Its Performance Evaluations

X. ZHANG, X. JIANG, S. HORIGUCHI
2007 IEICE transactions on electronics  
counterpart, as verified by an extensive simulation study that incorporates simultaneously the effects of process variations and on-chip inductance.  ...  We also propose a closed-form statistical models for evaluating the skew and delay of the Variant X-Tree CDN.  ...  The well-balanced H-Tree CDN has been widely adopted to eliminate the skew caused by unequal clock path lengths [9] , where the uncontrollable clock skew mainly comes from the variations in process parameters  ... 
doi:10.1093/ietele/e90-c.10.1909 fatcat:zrq4ghqbhjghpj3zfrqlfl6ivm

Impact of interconnect variations on the clock skew of a gigahertz microprocessor

Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas
2000 Proceedings of the 37th conference on Design automation - DAC '00  
The results show that the interconnect variations can cause up to 25% clock skew variability in a modern microprocessor design.  ...  In this paper we analyze the timing impact of several key statistically independent interconnect variations in a context-dependent manner by applying a previously reported interconnect variational order-reduction  ...  This is a very significant par of the clock skew budget and would indicate a need for a clock net redesign to increase its immunity to such fluctuations.  ... 
doi:10.1145/337292.337365 dblp:conf/dac/LiuNPS00 fatcat:jeul6klhlzhvhbxvntvb3twaje

A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting

Jonggab Kil, Jie Gu, Chris H. Kim
2006 Proceedings of the 2006 international symposium on Low power electronics and design - ISLPED '06  
This paper describes an interconnect technique for subthreshold circuits to improve global wire delay and reduce the delay variation due to PVT fluctuations.  ...  A clock distribution network using the proposed drivers shows an 89% reduction in 3σ clock skew value.  ...  clock skew caused by PVT variations.  ... 
doi:10.1145/1165573.1165590 dblp:conf/islped/KilGK06 fatcat:zmpyep3fovawzisv6pgtrempp4

A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting

Jonggab Kil, Jie Gu, C.H. Kim
2008 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
This paper describes an interconnect technique for subthreshold circuits to improve global wire delay and reduce the delay variation due to PVT fluctuations.  ...  A clock distribution network using the proposed drivers shows an 89% reduction in 3σ clock skew value.  ...  clock skew caused by PVT variations.  ... 
doi:10.1109/tvlsi.2007.915455 fatcat:ignwfxrxj5hbvgfq7g3bscejuy

A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting

Jonggab Kil, Jie Gu, Chris H. Kim
2006 ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design  
This paper describes an interconnect technique for subthreshold circuits to improve global wire delay and reduce the delay variation due to PVT fluctuations.  ...  A clock distribution network using the proposed drivers shows an 89% reduction in 3σ clock skew value.  ...  clock skew caused by PVT variations.  ... 
doi:10.1109/lpe.2006.4271809 fatcat:dalrkhrdana4bgktqo3rvarxry

Serial reconfigurable mismatch-tolerant clock distribution

Atanu Chattopadhyay, Zeljko Zilic
2009 Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09  
It suits a variety of applications, clock domain shapes and sizes using a modular standard cell approach that compensates intra-die temperature and process variances.  ...  By adding routing to the serial clock network, we permit post-silicon resizing and reshaping of clock domains.  ...  Increased power density in ICs can cause significant cross-die temperature fluctuation, or so called "hot spots" that alter transistor and interconnect behavior.  ... 
doi:10.1145/1629911.1630068 dblp:conf/dac/ChattopadhyayZ09 fatcat:75xmkzvfcjdphnoaxzsizbshfa

Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits

Xin Zhao, Jeremy R. Tolbert, Saibal Mukhopadhyay, Sung Kyu Lim
2012 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We propose a variation-aware methodology that controls both clock skew and slew to maximize F max and minimize clock power.  ...  In addition, clock networks in ULV circuits are highly sensitive to process variations.  ...  Hence, threshold voltage variability can cause a significant variation in clock skew and slew, thereby degrading the timing margins.  ... 
doi:10.1109/tcad.2012.2190825 fatcat:ixuu6oc75bdt3jf2hk3e4puitm

Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits

Xin Zhao, Jeremy R. Tolbert, Chang Liu, Saibal Mukhopadhyay, Sung Kyu Lim
2011 IEEE/ACM International Symposium on Low Power Electronics and Design  
We propose a variation-aware methodology that controls both clock skew and slew to maximize F max and minimize clock power.  ...  In addition, clock networks in ULV circuits are highly sensitive to process variations.  ...  Hence, threshold voltage variability can cause a significant variation in clock skew and slew, thereby degrading the timing margins.  ... 
doi:10.1109/islped.2011.5993615 fatcat:v6tfby3bfzg7jesqqk7yirjazq

Robust Clock Network Design Methodology for Ultra-Low Voltage Operations

Mingoo Seok, David Blaauw, Dennis Sylvester
2011 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
We also perform case studies of low voltage clock network design for a microprocessor and signal processing core.  ...  Robust design is a critical concern in ultra-low voltage operation due to large sensitivities to process and environmental variations.  ...  ACKNOWLEDGMENT The authors acknowledge the support of the Gigascale Systems Research Center, one of the five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation  ... 
doi:10.1109/jetcas.2011.2160753 fatcat:5zfwtniazfhlzlgdszz3xm5yw4

Over GHz low-power RF clock distribution for a multiprocessor digital system

Woonghwan Ryu, A.L.C. Wai, Fan Wei, Wai Lai Lai, Joungho Kim
2002 IEEE Transactions on Advanced Packaging  
Based on this analysis, a novel signal integrity design methodology for RF clock distribution systems is proposed. The clock skew created by process parameter variations are modeled and predicted.  ...  Finally, the RCD as a low power and high performance clocking method is demonstrated using HP's Advanced Design System (ADS) simulation, considering microwave frequency interconnection models and process  ...  Law, Nanyang Technology University, for their support for this work, L. K. Cheah and Dr. Mohaime, Gintic Institute of Manufacturing Technology, for their assistance in fabricating PCB, and C. K.  ... 
doi:10.1109/tadvp.2002.1017680 fatcat:udyxhg4n3jabtanernzrfivlry

Clock design of 300MHz 128-bit 2-way superscalar microprocessor

Fujio Ishihara, Christian Klinger, Ken-ichi Agawa
2000 Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00  
Combination of three different clock tuning methods is successfully applied to the entire clock tree and the clock skew is minimized efficiently within a limited design period.  ...  The shared clock wire configuration and clock buffer layout patterns over the whole die enhance the clock skew insensitivity to process fluctuation.  ...  Urakawa of Toshiba Corporation for planning clock distribution and tuning methodologies in the early stage of the die development and giving us instructive advice throughout the design period.  ... 
doi:10.1145/368434.368857 dblp:conf/aspdac/IshiharaKA00 fatcat:vbwp2paqi5fsdnhamryh46mene

Clock distribution networks in synchronous digital integrated circuits

E.G. Friedman
2001 Proceedings of the IEEE  
A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths.  ...  The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated  ...  This technique minimizes process-induced clock skew caused by asymmetric variations of the device parameters of the -channel and -channel MOSFETs.  ... 
doi:10.1109/5.929649 fatcat:eppzijpvzncvnpjzkgenkug6ni

Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks

Atanu Chattopadhyay, Zeljko Zilic
2012 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Routing clock lines serially allows optimal wire usage for clock networks by eliminating the redundant wires required to match path delays.  ...  The system uses a closed-loop synchronization phase to combine the clock skew reduction of an actively synchronized clock network with an open-loop operating phase that minimizes power consumption like  ...  ACKNOWLEDGMENT The authors would like to thank CMC Microsystems for providing access to design and manufacturing resources.  ... 
doi:10.1109/tvlsi.2011.2104982 fatcat:g2gfz5uwxje4xcokb6i7h4xxg4
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