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A Memory-Level Parallelism Aware Fetch Policy for SMT Processors

Stijn Everman, Lieven Eeckhout
2007 2007 IEEE 13th International Symposium on High Performance Computer Architecture  
This paper proposes an SMT fetch policy that takes into account the available memory-level parallelism (MLP) in a thread.  ...  The proposed MLP-aware fetch policy achieves better performance for MLP-intensive threads on an SMT processor and achieves a better overall balance between performance and fairness than previously proposed  ...  Acknowledgements The authors would like to thank the anonymous reviewers for their feedback.  ... 
doi:10.1109/hpca.2007.346201 dblp:conf/hpca/EyermanE07 fatcat:6uukg2gsaba6xgwf4e5nwf4uqi

Memory-level parallelism aware fetch policies for simultaneous multithreading processors

Stijn Eyerman, Lieven Eeckhout
2009 ACM Transactions on Architecture and Code Optimization (TACO)  
This article proposes an SMT fetch policy that takes into account the available memory-level parallelism (MLP) in a thread.  ...  MLP-aware fetch policies achieve better performance for MLP-intensive threads on SMT processors, leading to higher overall system throughput and shorter average turnaround time than previously proposed  ...  ACKNOWLEDGMENTS The authors would like to thank the anonymous reviewers for their valuable feedback and suggestions.  ... 
doi:10.1145/1509864.1509867 fatcat:qlpsbbotazavdcbdcfgjezxbj4

PEEP: Exploiting predictability of memory dependences in SMT processors

Samantika Subramaniam, Milos Prvulovic, Gabriel H. Loh
2008 High-Performance Computer Architecture  
We then propose the technique of Proactive Exclusion (PE) where the SMT fetch unit stops fetching from a thread when a memory dependence is predicted to exist.  ...  These strong results indicate that a fetch policy that is cognizant of future stalls considerably improves the throughput of an SMT machine.  ...  We are grateful for the constructive feedback provided by the anonymous reviewers.  ... 
doi:10.1109/hpca.2008.4658634 dblp:conf/hpca/SubramaniamPL08 fatcat:hsc2gpeagrar7mfnfqp7uawgeu

MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor [chapter]

Kenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhout
2009 Lecture Notes in Computer Science  
Comparing MLP-aware runahead threads against other fetch SMT policies in terms of STP for four-program workloads 0 1 2 3 4 5 6 vo rt ex ,p ar se r, cr af ty ,t w ol f fa ce re c, cr af ty ,v pr ,s ix tr  ...  Runahead threads do not block commit on a long-latency load but instead execute subsequent instructions in a speculative execution mode to expose memory-level parallelism (MLP) through prefetching.  ...  Acknowledgements We would like to thank the anonymous reviewers for their valuable comments.  ... 
doi:10.1007/978-3-540-92990-1_10 fatcat:b6twd4eo3nhadbjcr7gjvd54c4

PCOUNT: A power aware fetch policy in Simultaneous Multithreading processors

Lichen Weng, Gang Quan, Chen Liu
2011 2011 International Green Computing Conference and Workshops  
This paper proposes a power aware fetch policy PCOUNT, which evaluates the power consumption for two categories in SMT: computation resources and memory accessing resources.  ...  Moreover, fetch policies are proposed to assign priorities in the fetch stage to manage the shared resources. However, power consumption study is omitted in most fetch policies.  ...  The goal of this study is to develop a power aware fetch policy in SMT processors, such that the power consumption of different threads is evaluated independently.  ... 
doi:10.1109/igcc.2011.6008578 dblp:conf/green/WengQL11 fatcat:kzsk5tkyfnbspffz64ac7q2mu4

Runahead Threads to improve SMT performance

Tanausu Ramirez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero
2008 High-Performance Computer Architecture  
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded (SMT) processors.  ...  We compare an SMT architecture using RaT to both state-of-the-art static fetch policies and dynamic resource control policies.  ...  We would like to thank Dean Tullsen for his useful suggestions and help on improving this work.  ... 
doi:10.1109/hpca.2008.4658635 dblp:conf/hpca/RamirezPSV08 fatcat:ovcvq3z4h5a6xndteuguds7ma4

An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures

Wangyuan Zhang, Xin Fu, Tao Li, Jose Fortes
2007 2007 IEEE International Symposium on Performance Analysis of Systems & Software  
Simultaneous multithreaded (SMT) architectures exploit thread-level parallelism to improve overall processor throughput.  ...  To address this issue, we have developed a microarchitecture level soft error vulnerability analysis framework for SMT architectures.  ...  used in commercial processors [10, 11] to exploit thread-level parallelism.  ... 
doi:10.1109/ispass.2007.363747 dblp:conf/ispass/ZhangFLF07 fatcat:3qns4xdth5fdtl3xowy64gjevq

Per-thread cycle accounting in SMT processors

Stijn Eyerman, Lieven Eeckhout
2009 SIGARCH Computer Architecture News  
Second, a new class of thread-progress aware SMT fetch policies based on per-thread progress indicators enable system software level priorities to be enforced at the hardware level.  ...  This paper proposes a cycle accounting architecture for Simultaneous Multithreading (SMT) processors that estimates the execution times for each of the threads had they been executed alone, while they  ...  Acknowledgments The authors would like to thank the anonymous reviewers for their valuable comments and suggestions.  ... 
doi:10.1145/2528521.1508260 fatcat:qir3y4cob5dp5crixlaebpr2vq

Per-thread cycle accounting in SMT processors

Stijn Eyerman, Lieven Eeckhout
2009 Proceeding of the 14th international conference on Architectural support for programming languages and operating systems - ASPLOS '09  
Second, a new class of thread-progress aware SMT fetch policies based on per-thread progress indicators enable system software level priorities to be enforced at the hardware level.  ...  This paper proposes a cycle accounting architecture for Simultaneous Multithreading (SMT) processors that estimates the execution times for each of the threads had they been executed alone, while they  ...  Acknowledgments The authors would like to thank the anonymous reviewers for their valuable comments and suggestions.  ... 
doi:10.1145/1508244.1508260 dblp:conf/asplos/EyermanE09 fatcat:rl632osjnzgmxoxt6pmtditfs4

Per-thread cycle accounting in SMT processors

Stijn Eyerman, Lieven Eeckhout
2009 SIGPLAN notices  
Second, a new class of thread-progress aware SMT fetch policies based on per-thread progress indicators enable system software level priorities to be enforced at the hardware level.  ...  This paper proposes a cycle accounting architecture for Simultaneous Multithreading (SMT) processors that estimates the execution times for each of the threads had they been executed alone, while they  ...  Acknowledgments The authors would like to thank the anonymous reviewers for their valuable comments and suggestions.  ... 
doi:10.1145/1508284.1508260 fatcat:jkzumnjppnehhfzspsilz6isf4

Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures

Xin Fu, Wangyuan Zhang, Tao Li, José Fortes
2008 2008 37th International Conference on Parallel Processing  
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) processors.  ...  However, exploiting more parallelism yields high susceptibility to transient faults on a conventional IQ.  ...  In a dynamically scheduled SMT processor, the issue queue (IQ) is a key microarchitecture structure for extracting parallelism.  ... 
doi:10.1109/icpp.2008.23 dblp:conf/icpp/FuZLF08 fatcat:zk27gnhemrbcdglrcw2xdfbghu

PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors

Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi
2008 21st International Conference on VLSI Design (VLSID 2008)  
To this end, we have developed PTSMT: a tightly coupled power, performance and thermal exploration tool for SMT processors.  ...  While several performance simulation tools to explore the performance aspect of SMT processors early in their design phase exist, there is a lack of early power and performance evaluation tools for SMT  ...  Effect of Fetch Policies PTSMT allows the exploration of different policies for fetching instructions from the ready queues of hardware contexts, for SMT processors.  ... 
doi:10.1109/vlsi.2008.84 dblp:conf/vlsid/KannanGSDK08 fatcat:2ig3yoe6rzhvnfjqnuj36p3do4

Selection of the Register File Size and the Resource Allocation Policy on SMT Processors

Jesús Alastruey, Teresa Monreal, Francisco Cazorla, Víctor Viñals, Mateo Valero
2008 2008 20th International Symposium on Computer Architecture and High Performance Computing  
The second contribution of this work is a simple procedure that, for a given resource allocation policy, selects the PRF size that maximizes IPS and obtains for Hmean-wIPC a value close to its maximum.  ...  The performance impact of the Physical Register File (PRF) size on Simultaneous Multithreading processors has not been extensively studied in spite of being a critical shared resource.  ...  Memory-Level Parallelism aware (MLP-aware) tries to overlap the execution of independent long-latency loads, thus hiding memory access penalties [5] .  ... 
doi:10.1109/sbac-pad.2008.17 dblp:conf/sbac-pad/AlastrueyMCVV08 fatcat:qomh43sotrddjhf64qnbso5jn4

A survey of processors with explicit multithreading

Theo Ungerer, Borut Robič, Jurij Šilc
2003 ACM Computing Surveys  
Underutilization of a superscalar processor due to missing instruction-level parallelism can be overcome by simultaneous multithreading, where a processor can issue multiple instructions from multiple  ...  A multithreaded processor is able to pursue two or more threads of control in parallel within the processor pipeline.  ...  ACKNOWLEDGMENTS The authors would like to thank anonymous reviewers for many valuable comments.  ... 
doi:10.1145/641865.641867 fatcat:u6x7jdmkfvexnm3culskjsoxwi

An evaluation of speculative instruction execution on simultaneous multithreaded processors

Steven Swanson, Luke K. McDowell, Michael M. Swift, Susan J. Eggers, Henry M. Levy
2003 ACM Transactions on Computer Systems  
We also examine the effect of speculationaware fetch and branch prediction policies in the processor.  ...  to a superscalar processor.  ...  We attempt to improve SMT performance by reducing wrong-path speculative instructions, either by not speculating at all or by using speculation-aware fetch policies (including policies that incorporate  ... 
doi:10.1145/859716.859720 fatcat:wvglif7ijzct7bcc2hz75xoqpy
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