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SynFull: Synthetic traffic models capturing cache coherent behaviour

Mario Badr, Natalie Enright Jerger
2014 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)  
We propose SynFull, a synthetic traffic generation methodology that captures both application and cache coherence behaviour to rapidly evaluate NoCs.  ...  Current simulation methodologies for evaluating networkson-chip (NoCs) are not keeping pace with the increased complexity of our systems; architects often want to explore many different design knobs quickly  ...  Acknowledgements This research was funded by a gift from Intel. Additional support was provided by the Canadian Foundation for Innovation and the Ontario Research Fund.  ... 
doi:10.1109/isca.2014.6853236 dblp:conf/isca/BadrJ14 fatcat:katqdveu5zbmbiyo6urauhgv5e

SynFull

Mario Badr, Natalie Enright Jerger
2014 SIGARCH Computer Architecture News  
We propose SynFull, a synthetic traffic generation methodology that captures both application and cache coherence behaviour to rapidly evaluate NoCs.  ...  Current simulation methodologies for evaluating networkson-chip (NoCs) are not keeping pace with the increased complexity of our systems; architects often want to explore many different design knobs quickly  ...  Acknowledgements This research was funded by a gift from Intel. Additional support was provided by the Canadian Foundation for Innovation and the Ontario Research Fund.  ... 
doi:10.1145/2678373.2665691 fatcat:rujqncamz5f3hk7zupylfvbwc4

Functional and Performance Analysis of Network-on-Chips Using Actor-based Modeling and Formal Verification

Zeinab Sharifi, Mahdi Mosaffa, Siamak Mohammadi, Marjan Sirjani
2014 Electronic Communications of the EASST  
In order to analyze large NoCs we propose a scalable approachbased on compositional verification for estimating maximum end-to-end packet latency.The compositional approach is specific for the XY-routing  ...  Formal methods have gained moreattention as alternative ways for analyzing NoC designs.  ...  In [FTHJ09] an analytical method based on Markov chain stochastic processes is proposed for computation of mean latency of the end-to-end communications via a 2-dimensional mesh NoC.  ... 
doi:10.14279/tuj.eceasst.66.890 dblp:journals/eceasst/sharifiMMS13 fatcat:qaodfshiqjcdle2zqe6grxxydi

Static timing analysis for modeling QoS in networks-on-chip

Evgeni Krimer, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter, Mattan Erez
2011 Journal of Parallel and Distributed Computing  
Using a carefully derived and reduced Markov chain, the model can statically represent dynamic network state. Usage of the model in a placement optimization problem is shown as an example application.  ...  In particular, a model for the properties of packet delivery through the network is desirable. We present a methodology for packet-level static timing analysis in NoCs.  ...  Acknowledgments We thank the anonymous reviewers whose comments helped to significantly improve the paper. We also thank Prof.  ... 
doi:10.1016/j.jpdc.2010.10.003 fatcat:csmkzrugjzdk7jfzetlzcxdivu

Quantitative evaluation in embedded system design

Nicolas Coste, Holger Hermanns, Yvain Thonnart, Hubert Garavel, Richard Hersemeule, Meriem Zidouni
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
(qualitative properties) and to predict their performance (quantitative properties).  ...  This paper presents the work currently done in the Multival project (pôle de compétitivité mondial Minalogic), in which verification and performance evaluation tools developed at INRIA and Saarland University  ...  Performance Evaluation Flow in Multival Performance evaluation in the Multival project is based on the IMC (Interactive Markov Chains) formalism [3] , which combines the concepts of concurrency theory  ... 
doi:10.1145/1403375.1403399 fatcat:w6wjyw5qzvcc7mmimtg3ct3d6q

Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures

Nicolas Coste, Hubert Garavel, Holger Hermanns, Richard Hersemeule, Yvain Thonnart, Meriem Zidouni
2008 2008 Design, Automation and Test in Europe  
(qualitative properties) and to predict their performance (quantitative properties).  ...  This paper presents the work currently done in the Multival project (pôle de compétitivité mondial Minalogic), in which verification and performance evaluation tools developed at INRIA and Saarland University  ...  Performance Evaluation Flow in Multival Performance evaluation in the Multival project is based on the IMC (Interactive Markov Chains) formalism [3] , which combines the concepts of concurrency theory  ... 
doi:10.1109/date.2008.4484666 dblp:conf/date/CosteGHHTZ08 fatcat:xaxghr3zrzdafnitzvwcld5xrm

Packet-level static timing analysis for NoCs

Evgeni Krimer, Mattan Erez, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter
2009 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip  
Using a carefully derived and reduced Markov chain, the model can statically represent the dynamic network state and closely estimate the average latency of each flow.  ...  Networks -on-chip (NoCs) are used in a growing number of SoCs and multi-core processors, increasing the need for accurate and efficient modeling to aid the design of integrated systems.  ...  Acknowledgments We would like to thank Prof. Moshe Sidi for an interesting and fruitful discussion. This work was partly supported by European Research Council Starting Grant No. 210389.  ... 
doi:10.1109/nocs.2009.5071451 dblp:conf/nocs/KrimerEKKW09 fatcat:oxgirubwmbfh7m7wncvrsvlcie

Co-synthesis of a configurable SoC platform based on a network on chip architecture

Mário P. Véstias, Horácio C. Neto
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
In this paper, we propose an approach to the design space exploration of a configurable SoC (CSoC) platform based on a network on chip (NoC) architecture for the execution of dataflow dominated embedded  ...  The constant increase of gate capacity and performance of configurable hardware chips made it possible to implement systems-on-chip (SoC) able to tackle the demanding requirements of many embedded systems  ...  The algorithm stops when three consecutive Markov chains end with the same value. The length of the Markov chain is equal to the size of the neighborhood.  ... 
doi:10.1145/1118299.1118312 fatcat:bcsrk7psorhe5aj3qzm2ehpzpm

A scalable packet-switch architecture based on OQ NoCs for data center networks

Fadoua Hassen, Lotfi Mhamdi
2017 Computer Networks  
We assess the performance of the switch in terms of throughput, end-to-end latency and blocking probability using Markov chain analysis, and we propose an analytical model that integrates the various design  ...  In this paper, we present a highly scalable packet-switch for the DCN environment, in which we exploit the Network-on-Chip (NoC) design paradigm to replace the single-hop crossbars with multi-hop Switching  ...  In this context, we evaluate the impact of the switch size on the end-to-end packet latency.  ... 
doi:10.1016/j.comnet.2017.08.003 fatcat:g7og33fjjfcy5dn6y3lng5dbwe

Analytical Performance Models for NoCs with Multiple Priority Traffic Classes [article]

Sumit K. Mandal, Raid Ayoub, Michael Kishinevsky, Umit Y. Ogras
2020 arXiv   pre-print
Our approach consists of developing two novel transformations of queuing system and designing an algorithm which iteratively uses these two transformations to estimate end-to-end latency.  ...  Since NoCs play a vital role in system performance and power consumption, pre-silicon evaluation environments include cycle-accurate NoC simulators.  ...  This technique forms a Markov chain for a given queuing system, then analyzes this model in z-domain through probability generating functions (PGF).  ... 
arXiv:1908.02408v2 fatcat:3jyhnksu2vcc3inpfel3a7nt3y

An accurate and scalable analytic model for round-robin arbitration in network-on-chip

Erik Fischer, Gerhard P. Fettweis
2013 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)  
In this paper, we propose an accurate service time estimation model that is designed for round-robin arbiters. It is further employed to a queueing model for network-on-chip.  ...  Networkon-chip is a common solution for the interconnection of large processor arrays.  ...  Therefore, a state in the Markov chain is specified by a vector of length N i .  ... 
doi:10.1109/nocs.2013.6558403 dblp:conf/nocs/FischerF13 fatcat:t5ccahxaojagbfda7goeacmxzu

Feature - NoC emulation: a tool and design flow for MPSoC

N. Genko, D. Atienza, G. De Micheli, L. Benini
2007 IEEE Circuits and Systems Magazine  
Finally, we propose a validation flow for MPSoCs based on our flexible NoC emulation framework, which allows designers to explore and optimize a range of solutions, as well as quickly characterize performance  ...  We present a flexible hardware-software emulation framework implemented on an FPGA that is specially designed to suitably explore, evaluate and compare a wide range of NoC solutions with a very limited  ...  [8, 9] use VHDL-based cycle-accurate models to evaluate the latency, throughput and other features in mesh-based and hierarchical NoC topologies. Bertozzi et al.  ... 
doi:10.1109/mcas.2007.910029 fatcat:2czjohe4xvgvzp7plupv6twive

Ten Years of Performance Evaluation for Concurrent Systems Using CADP [chapter]

Nicolas Coste, Hubert Garavel, Holger Hermanns, Frédéric Lang, Radu Mateescu, Wendelin Serwe
2010 Lecture Notes in Computer Science  
Traditional performance models like Markov chains and queueing networks are not easy to apply for large-sized systems, mainly because they lack hierarchical composition and abstraction means.  ...  The design of models suited for performance and reliability analysis is challenging due to complexity and size of the modeled systems, in particular for those with a high degree of irregularity.  ...  About a decade ago, Cadp has been extended with performance evaluation capabilities, based on the Imc (Interactive Markov Chain) theory [2, 3] .  ... 
doi:10.1007/978-3-642-16561-0_18 fatcat:eenulhij7rfe7djagjri4cpaju

Mathematical formalisms for performance evaluation of networks-on-chip

Abbas Eslami Kiasari, Axel Jantsch, Zhonghai Lu
2013 ACM Computing Surveys  
An open research issue is a unified analytical model for a comprehensive performance evaluation of NoCs. To this end, this article reviews the attempts that have been made to bridge these formalisms.  ...  Also, the respective strengths and weaknesses of each technique and its suitability for a specific purpose are investigated.  ...  ACKNOWLEDGMENT The authors would like to thank the reviewers for their valuable comments and suggestions.  ... 
doi:10.1145/2480741.2480755 fatcat:wwlsqn7arng7hcgu4lxwbpdf3u

An analytical model for on-chip interconnects in multimedia embedded systems

Yulei Wu, Geyong Min, Dakai Zhu, Laurence T. Yang
2013 ACM Transactions on Embedded Computing Systems  
Driven by the motivation of evaluating on-chip interconnects in multimedia embedded systems, a new analytical model is proposed to investigate the performance of the fat-tree based on-chip interconnection  ...  Extensive simulation experiments are conducted to validate the accuracy of the model, which is then adopted as a cost-efficient tool to investigate the effects of bursty multimedia traffic with non-uniform  ...  a multi-state ergodic continuous-time Markov chain.  ... 
doi:10.1145/2536747.2536751 fatcat:ddhwx7pllnc2lgmrhlrqix6qjy
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