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A fast and low cost testing technique for core-based system-on-chip

Indradeep Ghosh, Sujit Dey, Niraj K. Jha
1998 Proceedings of the 35th annual conference on Design automation conference - DAC '98  
This paper proposes a new methodology for testing a core-based system-on-chip (SOC), targeting the simultaneous reduction of test area overhead and test application time.  ...  Application of the method to example SOCs demonstrates the ability to design highly testable SOCs with minimized test area overhead, minimized test application time, or a desired trade-off between the  ...  Acknowledgments: We would like to thank A. Raghunathan for his help with the example embedded systems and NEC CCRL for supporting I. Ghosh with a summer internship.  ... 
doi:10.1145/277044.277190 dblp:conf/dac/GhoshDJ98 fatcat:squmhwp62fdenl7s5m55b6uvee

Embedded software-based self-test for programmable core-based designs

A. Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, L. Chen, S. Dey
2002 IEEE Design & Test of Computers  
WITH THE GROWING popularity of system-ona-chip (SoC) architectures, demands for short time to market and rich functionality have driven design houses to adopt a new core-based SoC design flow.  ...  Because digital logic testers cannot do precise analog testing, externally testing mixed-Embedded Software-Based Self-Test for Programmable Core-Based Designs Embedded Systems 18 The programmable cores  ...  Using DSP-based testing techniques, Σ-∆ modulation principles, and some low-cost analog and mixed-signal DFT, the software-based self-testing paradigm can be generalized for testing analog and mixed-signal  ... 
doi:10.1109/mdt.2002.1018130 fatcat:fyyiaiaoj5dvzf6otfkzjqx25m

Embedded software-based self-testing for SoC design

A. Krstic, W. C. Lai, K. T. Cheng, L. Chen, S. Dey
2002 Proceedings - Design Automation Conference  
The advantages of this methodology include at-speed testing, low design-for-testability overhead and application of functional patterns in the functional environment.  ...  After the programmable core on a System-on-Chip (SoC) has been self-tested, it can be reused for testing on-chip buses, interfaces and other non-programmable cores.  ...  Mak, Intel on many stimulating discussions and useful insights on the topics in this paper.  ... 
doi:10.1145/514009.514010 fatcat:2nluc3xsorg2zegsuuliffxv7i

Embedded software-based self-testing for SoC design

A. Krstic, W. C. Lai, K. T. Cheng, L. Chen, S. Dey
2002 Proceedings - Design Automation Conference  
The advantages of this methodology include at-speed testing, low design-for-testability overhead and application of functional patterns in the functional environment.  ...  After the programmable core on a System-on-Chip (SoC) has been self-tested, it can be reused for testing on-chip buses, interfaces and other non-programmable cores.  ...  Mak, Intel on many stimulating discussions and useful insights on the topics in this paper.  ... 
doi:10.1145/513918.514010 dblp:conf/dac/KrsticLCCD02 fatcat:wanljgmetzfb7pncwaxcsm3x5e

Embedded hardware and software self-testing methodologies for processor cores

Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng
2000 Proceedings of the 37th conference on Design automation - DAC '00  
We propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests.  ...  Currently, Built-In Self-Test (BIST) is the primary self-test methodology available and is widely used for testing embedded memory cores.  ...  In addition to the test overhead required by the insertion of BIST structures, hardware-based logic BIST techniques must be accompanied by design changes required for making the processor-under-test random-pattern-testable  ... 
doi:10.1145/337292.337599 dblp:conf/dac/ChenDSSC00 fatcat:m7k46u6t3ve37gn67e3bety56e

NEW AUTOMATIC TESTING ARCHITECTURE FOR INTEGRATED CIRCUITS

Sherif Anas, Mohamed El-Mahlawy, Ehab El-Sehely, Al-Emam Ragab
2006 The International Conference on Electrical Engineering  
In this paper, a complete example for BIST (Built-In Self-Test) boundary scan architecture and 16-bit multiplier as the CUT is presented.  ...  Adding BIST boundary scan capabilities to the digital VLSI integrated circuit design makes the electronic card testable from five pins TMS, TCK, TDI, TDO and TRST* that is optional.  ...  The test circuitry is built in the VLSI chip with the slave controller (TAP controller). The personal computer, that is able to be portable, is used as a master programmable controller.  ... 
doi:10.21608/iceeng.2006.33556 fatcat:dv4eos6olnetjbkgk6oztrn7u4

Cost and benefit models for logic and memory BIST

Juin-Ming Lu, Cheng-Wen Wu
2000 Proceedings of the conference on Design, automation and test in Europe - DATE '00  
However, BIST is a good choice for memory cores in general.  ...  In our cost and benefit models for BIST, we take into consideration the design verification time and test development time associated with testability.  ...  Introduction Built-in self-test (BIST) is receiving growing attention with the advent of core-based system-on-chip (SOC) design, which is a natural sequel of deep-submicron VLSI technology.  ... 
doi:10.1145/343647.343900 fatcat:iy3wdsld5zh6rhvlpbvm24um2q

Comments on "Filling algorithms and analyses for layout density control"

Rung-Bin Lin
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The experimental results show that the use of FSA-based testability analysis facilitates low test overheads and test application times without sacrificing the test coverage of the embedded cores.  ...  Index Terms-Design for testability, synthesis for testability, systemon-a-chip, test synthesis. 0278-0070/02$17.00 © 2002 IEEE  ...  ACKNOWLEDGMENT The authors would like to thank the Associate Editor and the anonymous reviewers for their helpful comments and suggestions.  ... 
doi:10.1109/tcad.2002.802262 fatcat:lif5d7bimjbezieckvo2t3b5uu

A synthesis-for-transparency approach for hierarchical and system-on-a-chip test

K. Chakrabarty
2003 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
This approach can also be applied to system-on-a-chip designs in which synthesizable models are available for the embedded cores.  ...  We propose a new synthesis-for-test approach in which multiplexers are embedded in the behavioral models of the various modules constituting a hierarchical system.  ...  Testability-driven behavioral synthesis can produce area-efficient designs with low test-related overhead [23] .  ... 
doi:10.1109/tvlsi.2003.810784 fatcat:2vmmyslctngy7jnmxbnxq2t3zu

Testing Core-Based System-on-a-Chip Designs

Xiaoqing Wen, Kewal K. Saluja, Kozo Kinoshita
2001 The Journal of Reliability Association of Japan  
This paper reviews a general strategy for testing core-based systemon-a-chip designs.  ...  The strategy includes isolating cores from each other to reduce total test complexity, using the best method for testing each individual core, and starting test development for a core early in its design  ...  Sanada at NEC for the opportunity of preparing this paper.  ... 
doi:10.11348/reajshinrai.23.4_371 fatcat:zqumaqcauvd27d5zavvqzovo6u

Instruction-level DFT for testing processor and IP cores in system-on-a-chip

Wei-Cheng Lai, Kwang-Ting Cheng
2001 Proceedings of the 38th conference on Design automation - DAC '01  
Self-testing manufacturing defects in a system-on-a-chip (SOC) by running test programs using a programmable core has several potential benefits including, at-speed testing, low DfT overhead due to elimination  ...  The experimental results show that with the added test instructions, a complete fault coverage for testable path delay faults can be achieved with a greater than 20% reduction in the program size and the  ...  With the added test instructions, embeddedsoftware-based self-testing can achieve a higher fault cover-age, shorter test generation time and smaller and faster test programs with a very low area overhead  ... 
doi:10.1145/378239.378282 dblp:conf/dac/LaiC01 fatcat:jcqs5a6xp5gqnia7x54ooddz2m

The DFA/DFT‐based hacking techniques and countermeasures: Case study of the 32‐bit AES encryption crypto‐core

Mouna Karmani, Noura Benhadjyoussef, Belgacem Hamdi, Mohsen Machhout
2021 IET Computers & Digital Techniques  
Here, a 32-bit AES crypto-core is used as a case study in order to analyse the DFA-and the DFT-based Hacking techniques.  ...  Therefore, the embedded system testing is considered earlier during the design process and testability is used as one of the objectives for evaluating safety-critical embedded system designs.  ...  In order to simplify tests, special hardware has to be added such that testing becomes easier. The process of designing for a better testability is called design for testability (DFT).  ... 
doi:10.1049/cdt2.12013 fatcat:zzpzutktundtlc3q5nathppntq

System-on-chip testability using LSSD scan structures

K. Zarrineh, S.J. Upadhyaya, V. Chickermane
2001 IEEE Design & Test of Computers  
Acknowledgment This work was supported and developed at IBM, Endicott, N.Y.  ...  Enhancing system-on-chip testability We review techniques for enhancing the testability of embedded memories, cores, and chips using the LSSD boundary scan methodology.  ...  Thus several scattered embedded memories in the design can share one memory BIST unit, incurring only a very low wiring overhead.  ... 
doi:10.1109/54.922805 fatcat:h5dpo2aoqrddxdqtfxvvevoe3a

BIST for systems-on-a-chip

Hans-Joachim Wunderlich
1998 Integration  
Core-providers offer RISC-kernels, embedded memories, DSPs, and many other functions, and built-in self-test is the appropriate method for testing complex systems composed of different cores.  ...  In this paper, we overview BIST methods for different types of cores and present advanced BIST solutions.  ...  For this scheme, automation is as easy as scan design, the hardware overhead is very low, and no costs for BIST control are involved.  ... 
doi:10.1016/s0167-9260(98)00021-2 fatcat:qenkm6odojampcjqguhbco6l6m

Analysis of Recent Secure Scan Test Techniques

Cheng Xing, Sungju Park, Ji Zhao
2016 Journal of Software Engineering and Applications  
This paper meticulously selects three current scan test techniques, analyses their advantages and disadvantages and also compares them in security and area overhead.  ...  Side channel attack may result in user key leakage as scan test techniques are applied for cryptographic chips. Many secure scan designs have been proposed to protect the user key.  ...  To achieve the expected trade-off among testability, security and test cost, user can select the proper technique or the combination of them.  ... 
doi:10.4236/jsea.2016.93008 fatcat:qlpum7uhqvbnbnu5d2pob4rx54
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