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Seven GHz high gain 0.18 μm CMOS Gilbert downconverter with wide-swing cascode current mirrors

Sheng-Che Tseng, Chinchun Meng, Guo-Wei Huang
2008 Microwave and optical technology letters (Print)  
In the in-band range, the locked signal tracks the low-phase-noise reference signal and provides the obvious improvement of phase noise about 6 dB.  ...  The final f max /f min ratio is 6.5, and the output spectrums at maximum and minimum input frequency are shown in Figures 5(a) and 5(b), respectively.  ...  downconversion micromixer with low-voltage cascode current mirrors at both transconductor and load stages has been implemented using the 0.18-m CMOS technology in this article.  ... 
doi:10.1002/mop.23095 fatcat:aevvkkxk2zatlpb7msnrm2cxyu

Bit Error Performance of APD and SPAD Receivers in Optical Wireless Communication

Hiwa Mahmoudi, Horst Zimmermann
2021 Electronics  
In turn, and in combination with fully integrated optical receivers, reduction of cost and increased comfort can be achieved.  ...  a standing-wave model for the isolation and passivation stack, is extended.  ...  They, however, suffer also from a low responsivity of the photodetector in 0.18 and 0.13 µm CMOS, respectively.  ... 
doi:10.3390/electronics10222731 fatcat:4ohkx7fvy5abfbnu5733rthasq

Physical design challenges to nano-CMOS circuits

Kazuya Masu, Noboru Ishihara, Noriaki Nakayama, Takashi Sato, Shuhei Amakawa
2009 IEICE Electronics Express  
First, in line with variation-aware design, a novel ingenious method of measuring variations in subthreshold characteristics is described.  ...  There are many challenges inherent in the design of nano-CMOS. This paper describes our recent work relating to the physical design of CMOS circuits.  ...  Regarding chip design and fabrication in this work, we are indebted to VDEC, in collaboration with Cadence Design Systems, Inc. and Synopsys, Inc.  ... 
doi:10.1587/elex.6.703 fatcat:fwyoecgnhbarlfxmqsjmjtjo6a

Novel pure‐metal tri‐axis CMOS‐MEMS accelerometer design and implementation

Jung‐Hung Wen, Weileum Fang
2021 Micro & Nano Letters  
This work proposed a pure-metal, single-proof-mass structure fabricated by the standard 0.18 μm one-poly-silicon six-metal (1P6M) CMOS process along with one inhouse post-CMOS wet-etching approach.  ...  The fabricated tri-axis accelerometer reveals stable and consistent results and exemplifies a potential platform design for the highly integrated monolithic CMOS-MEMS system-on-chip applications.  ...  In this design, a general-purpose inertial sensor is considered to implement by the standard TSMC 0.18 μm 1P6M CMOS process.  ... 
doi:10.1049/mna2.12014 fatcat:xsvritixr5cungrsu2nguxgaoq

A Review of Modern CMOS Transimpedance Amplifiers for OTDR Applications

Agata Romanova, Vaidotas Barzdenas
2019 Electronics  
The work presents a review of modern CMOS transimpedance amplifiers (TIAs) in the context of their application for low-cost optical time-domain reflectometry (OTDR).  ...  A detailed discussion is given on a representative set of approaches reported in the literature and the figure of merit (FOM) is introduced as a unified basis for performance comparison.  ...  matching Jun-De Jin [9], 2006 0.18 µm 51.0 30.5 60.1 @ 1.8V 34.3 0.048 4 cascaded CS-stages with PIP Park, Oh [15] 1 , 2007 0.18 µm 64 2.1 50 @ 1.8V 33.2 2.76 differential, CG input  ... 
doi:10.3390/electronics8101073 fatcat:f5s7xcxrbjhuxlqlays2kltwza

A Wideband Noise and Harmonic Distortion Canceling Low-Noise Amplifier for High-Frequency Ultrasound Transducers

Yuxuan Tang, Yulang Feng, He Hu, Cheng Fang, Hao Deng, Runxi Zhang, Jun Zou, Jinghong Chen
2021 Sensors  
A high-frequency ultrasound (HFUS) and photoacoustic (PA) imaging front-end, including the proposed LNA and a variable gain amplifier (VGA), was designed and fabricated in a 180 nm CMOS process.  ...  This paper presents a wideband low-noise amplifier (LNA) front-end with noise and distortion cancellation for high-frequency ultrasound transducers.  ...  Funding: This research received no external funding. Institutional Review Board Statement: Not applicable. Informed Consent Statement: Not applicable.  ... 
doi:10.3390/s21248476 pmid:34960568 pmcid:PMC8703952 fatcat:rkdqgscpvzfapd63kgoompbkze

A Low-Power Current-Reuse LNA for 3D Ultrasound Beamformers

2021 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
The LNA was fabricated in a 0.18-µm CMOS process with only 0.0056 mm 2 . The measured results show a gain of 21 dB and a bandwidth of 9 MHz.  ...  The supply current is 85 µA with a 1.8-V power supply, which is competitive with conventional LNAs by finer CMOS process.  ...  Therefore, design for stability can be treated in the same manner as an open-loop differential LNA. Measurement Results The proposed LNA was designed and fabricated in a 0.18µm SOI CMOS process.  ... 
doi:10.1587/transfun.2020gcp0011 fatcat:5bl4rzkiangeziphtp6brxgnyy

12.1 3D ultrasonic gesture recognition

Richard J. Przybyla, Hao-Yen Tang, Stefon E. Shelton, David A. Horsley, Bernhard E. Boser
2014 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)  
Figure 12.1.7 shows a micrograph of the readout IC, which is fabricated in a 0.18μm CMOS process with 32V transistors. For a 1m maximum range, the system presented here uses 13.6μJ per measurement.  ...  The 450μm diameter piezoelectric micromachined ultrasound transducers (pMUTs) used in this work are made up of a 2.2μm thick AlN/Mo/AlN/Al stack deposited on a Si wafer and released with a back-side through-wafer  ...  Figure 12.1.7 shows a micrograph of the readout IC, which is fabricated in a 0.18μm CMOS process with 32V transistors. For a 1m maximum range, the system presented here uses 13.6μJ per measurement.  ... 
doi:10.1109/isscc.2014.6757403 dblp:conf/isscc/PrzybylaTSHB14 fatcat:lc7te32wvvbyzgfx3qcvdbvmri

A 24-Gb/s 27 ¿ 1 Pseudo Random Bit Sequence Generator IC in 0.13 ¿m Bulk CMOS

Franz Weiss, Hans-dieter Wohlmuth, Daniel Kehrer, Arpad Scholtz
2006 Proceedings of ESSCIRC  
The circuit features a trigger output which allows to trigger the eye or the sequence pattern. The circuit is manufactured in 0.13 µm bulk CMOS technology and draws 183 mA at 1.5 V supply voltage.  ...  This work presents a 24 Gb/s pseudo random bit sequence (PRBS) generator with a sequence length of 2 7 − 1 .  ...  Five stacked transistors at low CMOS supply voltage results in a very low voltage headroom for each transistor and a slower cell.  ... 
doi:10.1109/esscir.2006.307482 fatcat:mgqq7y3w2jekbpwstwsxeqo36u

2020 Index IEEE Solid-State Circuits Letters Vol. 3

2020 IEEE Solid-State Circuits Letters  
., +, LSSC 2020 102-105 A 0.0082-mm², 192-nW Single BJT Branch Bandgap Reference in 0.18-μm CMOS.  ...  Chen, K., +, LSSC 2020 21-24 Compensation A 0.0082-mm², 192-nW Single BJT Branch Bandgap Reference in 0.18-μm CMOS.  ... 
doi:10.1109/lssc.2021.3051791 fatcat:mnafvr7rwnaffepmblvu6cewvi

High-density mapping of brain slices using a large multi-functional high-density CMOS microelectrode array system

Vijay Viswam, Raziyeh Bounik, Amir Shadmani, Jelena Dragas, Marie Obien, Jan Muller, Yihui Chen, Andreas Hierlemann
2017 2017 19th International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS)  
We present a CMOS-based high-density microelectrode array (HD-MEA) system that enables high-density mapping of brain slices in-vitro with multiple readout modalities.  ...  The 4.48×2.43 mm 2 array consists of 59,760 micro-electrodes at 13.5 µm pitch (5487 electrodes/mm 2 ).  ...  A. Shadmani received individual support through FP7-MTN "EngCaBra" (Contract 264417).  ... 
doi:10.1109/transducers.2017.7994006 pmid:28868212 pmcid:PMC5580803 fatcat:45onrfmsk5bppab7xuhjbmjoyi

Inductorless 8.9 mW 25 Gb/s 1:4 DEMUX and 4 mW 13 Gb/s 4:1 MUX in 90 nm CMOS

Takayuki Sekiguchi, Shuhei Amakawa, Noboru Ishihara, Kazuya Masu
2010 JSTS Journal of Semiconductor Technology and Science  
The MUX/DEMUX mainly consists of differential pseudo-NMOS. In these MUX/DEMUX circuits, logic swing is nearly rail-torail, and a low V dd .  ...  A low-power inductorless 1:4 DEMUX and a 4:1 MUX for a 90 nm CMOS are presented.  ...  ACKNOWLEDGMENTS This study was partially supported by KAKENHI, MIC.SCOPE, STARC, and VDEC in collaboration with Agilent Technologies Japan, Ltd., Cadence Design Systems, Inc. and Mentor Graphics, Inc.  ... 
doi:10.5573/jsts.2010.10.3.176 fatcat:hlcbp7kxrfgdnb7llujk2ahqqq

A design methodology for programmable-gain low-noise TIA in CMOS

Agata Romanova, Vaidotas Barzdenas
2021 Journal of Electrical Engineering  
The work reports on the design of an area-efficient inductor-less low-noise CMOS transimpedance amplifier suitable for entry-level optical time-domain reflectometers.  ...  The work suggests a novel approach for implementing a programmable-gain in capacitive feedback TIA with an independent adjustment of the low- and high-frequency behavior using the input stage biasing impedance  ...  Results The proposed amplifier was designed and optimized using TSMC 0.18 µm CMOS process.  ... 
doi:10.2478/jee-2021-0021 fatcat:s2sq3qb4bnbt5h5ed3jkszimsy

An Optical Filter-Less CMOS Image Sensor with Differential Spectral Response Pixels for Simultaneous UV-Selective and Visible Imaging

Yhang Ricardo Sipauba Carvalho da Silva, Rihito Kuroda, Shigetoshi Sugawa
2019 Sensors  
The developed CIS has a pixel pitch of 5.6 µm and exhibits 172 µV/e− conversion gain, 131 ke− full well capacity (FWC), and 92.3 dB dynamic range.  ...  The developed CIS is composed by high and low UV sensitivity pixel types, arranged alternately in a checker pattern. Both pixel types were designed to have matching sensitivities for non-UV light.  ...  Funding: This research received no external funding. Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/s20010013 pmid:31861428 pmcid:PMC6983105 fatcat:27rkwerh4fhylpk7vkqwcp2bb4

RF/wireless-interconnect: The next wave of connectivity

SaiWang Tam, Mau-Chung Frank Chang
2011 Science China Information Sciences  
In the era of the nanometer CMOS technology, due to stringent system requirements in power, performance and other fundamental physical limitations (such as mechanical reliability, thermal constraints,  ...  To overcome such challenges, we first explore the use of multiband RF/wireless-interconnects which can communicate simultaneously through multiple frequency bands with low power signal transmission, reconfigurable  ...  Figure 11 11 Schematic of the RF-interconnect implemented in a 3D 0.18 µm CMOS process.  ... 
doi:10.1007/s11432-011-4225-8 fatcat:ndqip657abfx7mxusorw5zqhp4
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