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A low-cost jitter measurement technique for BIST applications

Jui-Jer Huang, Jiun-Lang Huang
2003 Proceedings of the 7th International Conference on Properties and Applications of Dielectric Materials (Cat No 03CH37417) ATS-03  
In this paper, we present a technique to measure the RMS period jitter of the signal under test.  ...  Currently, SPICE simulation results show less than 5% error for RMS jitter values ranging from 40 to 60 ps.  ...  In this paper, we propose an RMS period jitter measurement technique for BIST applications.  ... 
doi:10.1109/ats.2003.1250833 dblp:conf/ats/HuangH03 fatcat:tyk2v5affjggll4dfuawcukaae

Mixed signal DFT: a concise overview

B. Kaminska, K. Arabi
2003 ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)  
An introduction to practical DFT techniques for data converters (A/D and D/A) follow. An overview of IEEE P1149.4 analog test bus standard concludes the embedded tutorial.  ...  Special consideration is given to the possible DFT techniques for Phase-Locked Loops (PLLs) with associated implications on test coverage, performance, cost, and time to market.  ...  There are some applications where the absolute jitter is important, for example in clock synthesis circuits; there is a need for a use of a jitter-free or low jitter reference signal.  ... 
doi:10.1109/iccad.2003.159752 fatcat:k2o6o2gzufcrvcdxvmjkfdrkby

12Gbps SerDes Jitter Tolerance BIST in production loopback testing with enhanced spread spectrum clock generation circuit

Yi Cai, Liming Fang, Ivan Chan, Max Olsen, Kevin Richter
2013 2013 IEEE International Test Conference (ITC)  
We designed and tested an on-chip BIST test for high speed SerDes devices. Jitter Tolerance testing is a critical way to stress the SerDes receivers.  ...  A jitter free loopback test hardly represents the real application environment.  ...  Our goal is to provide a precise, at speed, and yet low cost solution for jitter tolerance test, so the DFT overhead needs to be very low.  ... 
doi:10.1109/test.2013.6651882 dblp:conf/itc/CaiFCOR13 fatcat:oq7yhlpcfbdrhkwkaicviorg4e

Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates

A. Ivanov, F. Lombardi, C. Metra
2004 IEEE Design & Test of Computers  
For this special issue, we've selected four articles to cover a wide spectrum of techniques and applications critical to testing at multiGbps rates.  ...  Recent years have seen the rapidly growing prominence of new techniques for testing ICs and systems with innovative features to allow high quality and fast test time.  ...  For example, researchers have advocated novel hybrid arrangements (a combination of BIST and ATE) as a possible alternative to speeding up test application time.  ... 
doi:10.1109/mdt.2004.31 fatcat:hgk624c2erbr7dsxolycrxu3jy

Analog and Mixed-Signal Test [chapter]

Haralampos-G Stratigopoulos, Bozena Kaminska
2016 Electronic Design Automation for IC System Design, Verification, and Testing  
For these reasons, measuring jitter exactly at the PLL output using BIST is the recommended method, especially for multi-GHz PLLs that may have RMS jitter as low 0.1-5 ps.  ...  Finally, BIST techniques to measure the jitter transfer function of PLLs are described in [212, 213] .  ... 
doi:10.1201/b19569-29 fatcat:22awilc5urewzhciqaymnyriey

Guest Editorial: Special Issue on Analog, Mixed-Signal, RF, and MEMS Testing

Hsiu-Ming Chang, David C. Keezer
2012 Journal of electronic testing  
Papers 5 to 7 focus on techniques for generating accurate and low-cost test signals.  ...  In paper 8, Kulovic and Margala introduce a technique for on-chip voltage measurement.  ...  Papers 5 to 7 focus on techniques for generating accurate and low-cost test signals.  ... 
doi:10.1007/s10836-012-5330-3 fatcat:zolhbokpefbupc2maj22ebg3mi

Recent Advances in Analog, Mixed-Signal, and RF Testing

Kwang-Ting (Tim) Cheng, Hsiu-Ming (Sherman) Chang
2010 IPSJ Transactions on System LSI Design Methodology  
This paper provides an overview of cost-effective test techniques that either enhance circuit testability, or enable built-in self-test (BIST) for integrated AMS/RF frontends.  ...  As a result, design for testability (DfT), combined with automatic test stimuli generation, has gradually become a necessity to ensure test quality at an affordable cost.  ...  be obtained in a low-cost fashion.  ... 
doi:10.2197/ipsjtsldm.3.19 fatcat:ta4eaij36vft7f6qkjvxbmpz4u

A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters

Shalabh Goyal, Abhijit Chatterjee, Michael Purtell
2007 Journal of electronic testing  
Testing high-speed A/D converters for dynamic specifications needs test equipment running at high frequency.  ...  During production testing, the devices are tested on the low-cost test set-up.  ...  In [13, 14] , authors present a methodology to measure true SNR of A/D converters by measuring internal jitter using a time differential sampling technique and total jitter by dual-SNR technique.  ... 
doi:10.1007/s10836-006-9523-5 fatcat:gsa33veswje2rgjrasfcorlmvu

Two methods for 24 Gbps test signal synthesis

D C Keezer, C E Gray
2011 2011 Design, Automation & Test in Europe  
The residual timing errors are dominated by jitter. Typical random jitter (RJ) is about 1.17ps to 1.4ps (RMS) including system measurement errors for the two methods.  ...  Deterministic Jitter (DJ) is between 2.4ps and 8.5ps. Total jitter (TJ) ranges between 18.9ps and 28.2ps at a bit-error-rate BER=10 -12 .  ...  Some relief from this dilemma is obtained through the application of design-for-test (DFT) and built-in self-test (BIST) techniques.  ... 
doi:10.1109/date.2011.5763288 dblp:conf/date/KeezerG11 fatcat:ysw3ymmxafdrhkqgzco6ewwwzq

Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications

Wei-Zen Chen, Guan-Sheng Huang
2008 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
This PRWG can be used as a low-cost substitute for external parallel test pattern generators.  ...  This paper presents the design of a low-power programmable pseudorandom word generator (PRWG) and a low-noise clock multiplier unit (CMU) for high-speed SerDes applications.  ...  ACKNOWLEDGMENT The authors wish to thank CIC for chip fabrication.  ... 
doi:10.1109/tcsi.2008.916507 fatcat:5ifcpj2safa7xco77rt4cafn24

Timing Jitter and Modulation Profile Extraction for Spread-Spectrum Clocks

Jenchien Hsu, Chauchin Su
2010 IEEE Transactions on Instrumentation and Measurement  
This paper presents a built-in jitter measurement approach for measuring the timing jitter of spread-spectrum clocks (SSCs) and a jitter estimation method for validating the approach.  ...  Because of the lack of dedicated measurement instruments for SSC timing jitter measurement, the jitter estimation method is proposed to correlate SSC and non-SSC jitter.  ...  To reduce the testing cost, a built-in self test (BIST) is considered a feasible alternative.  ... 
doi:10.1109/tim.2009.2025992 fatcat:zdwtptnkqbbkziwhzdritzoipa

On-chip Jitter Measurement Using Vernier Ring Time-to-Digital Converter

Jianjun Yu, Fa Foster Dai
2010 2010 19th IEEE Asian Test Symposium  
This on-chip jitter measurement scheme can measure a large jitter with a fine resolution smaller than 8ps.  ...  This paper presents an on-chip jitter measurement technique based on the Vernier ring time-do-digital converter (VRTDC).  ...  Recently, the time-to-digital converters (TDCs) have been used in many on-chip jitter measurement macros and BIST applications [1] [2] [3] .  ... 
doi:10.1109/ats.2010.38 dblp:conf/ats/YuD10 fatcat:ao55ktw6ebfsda3tfolwjgy3ay

Stretching the limits of FPGA SerDes for enhanced ATE performance

A M Majid, D C Keezer
2010 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)  
Exploiting recent advances in FPGA SerDes, the test module is able to generate very high (multi-GHz) data rates at a relatively low cost.  ...  In this paper we demonstrate multiplexing logic to generate higher data rates (up to 10Gbps) and a low-jitter buffered loopback path to carry high speed signals from the DUT back to the DUT.  ...  ACKNOWLEDGMENT This work was conducted as a joint R&D project between Georgia Tech and IBM Canada. System level tests were performed at the Georgia Tech High-Speed Test Lab.  ... 
doi:10.1109/date.2010.5457212 dblp:conf/date/MajidK10 fatcat:7rkgbh5jrneqbcdqrfri6lqlwq

Efficient BIST scheme for A∕D converters

K. Kim, Y.-J. Kim, Y.-S. Shin, D. Song, S. Kang
2005 IEE Proceedings - Circuits Devices and Systems  
In the paper, an efficient low-cost built-in self-test (BIST) scheme is developed for testing A/D converters.  ...  The reason for this is that analogue testing for high quality requires substantial testing costs although the analogue portion in a whole chip or in a system is usually very small.  ...  ., Chatterjeee, A., and Nagi, N.: 'Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling'.  ... 
doi:10.1049/ip-cds:20041171 fatcat:pwj7xvk25fd63mh6ayaalnk2ci

An all-digital built-in self-test technique for transfer function characterization of RF PLLs

Ping-Ying Wang, Hsiu-Ming Chang, Kwang-Ting Cheng
2011 2011 Design, Automation & Test in Europe  
This paper presents an all-digital built-in selftest (BIST) technique for characterizing the error transfer function of RF PLLs.  ...  The silicon characterization results at 3.6GHz reported by this BIST solution and by explicit measurement have a root-mean-square difference of 0.375dB only.  ...  ACKNOWLEDGMENTS The authors acknowledge the funding support and the measurement environment provided by MediaTek, Inc., HsinChu, Taiwan.  ... 
doi:10.1109/date.2011.5763063 dblp:conf/date/WangCC11 fatcat:xb6nl2yh3fhl3mtlmqmbuz5lpq
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