Filters








2,189 Hits in 3.9 sec

A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors

A. Falcon, A. Ramirez, M. Valero
10th International Symposium on High Performance Computer Architecture (HPCA'04)  
Simultaneous Multithreading (SMT) is an architectural technique that allows for the parallel execution of several threads simultaneously.  ...  In this paper we demonstrate that the simultaneous sharing of the fetch unit, apart from increasing the complexity of the fetch unit, can be counterproductive in terms of performance.  ...  Section 3 describes SMT fetch architectures needed to fetch from one thread and from many threads, as well as the high-performance, low complexity fetch units we propose for SMT.  ... 
doi:10.1109/hpca.2004.10003 dblp:conf/hpca/FalconRV04 fatcat:ugjdcpgbwzfvtidmf7yiftx5mq

Simultaneous multithreading: a platform for next-generation processors

S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, R.L. Stamm, D.M. Tullsen
1997 IEEE Micro  
We also thank Jennifer Anderson of DEC Western Research Laboratory for copies of the SpecFP95 benchmarks, parallelized by the most recent version of the SUIF compiler, and Sujay Parekh for comments on  ...  Acknowledgments We thank John O'Donnell of Equator Technologies, Inc. and Tryggve Fossum of Digital Equipment Corp. for the source to the Alpha AXP version of the Multiflow compiler.  ...  This performance also comes with a very low hardware cost.  ... 
doi:10.1109/40.621209 fatcat:zmx4yx2flnfazi3b6zdwhavnam

Dynamic Fetch Engine for Simultaneous Multithreaded Processors [chapter]

Tzung-Rei Yang, Jong-Jiann Shieh
2004 Lecture Notes in Computer Science  
While the fetch unit has been identified as one of the major bottlenecks of Simultaneous Multithreading architecture, several fetch schemes were proposed by prior works to enhance the fetching efficiency  ...  We proposed a dynamic fetch scheme which gives the long latency bound thread higher priority while the RUU or LSQ is under low usage.  ...  [7] proposed a fetch scheme that uses both fetch prioritizing and fetch gating for simultaneous multithreading processors.  ... 
doi:10.1007/978-3-540-30102-8_41 fatcat:2lwsbwdvunfnpecaf4piarvbim

Exploiting choice

Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm
1996 SIGARCH Computer Architecture News  
In previous work we demonstrated the performance potential of simultaneous multithreading, based on a somewhat idealized model.  ...  This speedup is enhanced by an advantage of multithreading previously unexploited in other architectures: the ability to favor for fetch and issue those threads most efficiently using the processor each  ...  Acknowledgments We would like to thank Tryggve Fossum for his support of this work and for numerous suggestions.  ... 
doi:10.1145/232974.232993 fatcat:ua5np5knqbb5fa2moodykmc25e

Exploiting choice

Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm
1996 Proceedings of the 23rd annual international symposium on Computer architecture - ISCA '96  
In previous work we demonstrated the performance potential of simultaneous multithreading, based on a somewhat idealized model.  ...  This speedup is enhanced by an advantage of multithreading previously unexploited in other architectures: the ability to favor for fetch and issue those threads most efficiently using the processor each  ...  Acknowledgments We would like to thank Tryggve Fossum for his support of this work and for numerous suggestions.  ... 
doi:10.1145/232973.232993 dblp:conf/isca/TullsenEELLS96 fatcat:rbtgwitvlrce3mraejgp4tm4hi

Multithreaded Processors

T. Ungerer
2002 Computer journal  
Underutilization of a superscalar processor due to missing instruction-level parallelism can be overcome by simultaneous multithreading, where a processor can issue multiple instructions from multiple  ...  Simultaneous multithreaded processors combine the multithreading technique with a wideissue superscalar processor such that the full issue bandwidth is utilized by potentially issuing instructions from  ...  be followed (high confidence) or both continuations should be followed simultaneously (low confidence).  ... 
doi:10.1093/comjnl/45.3.320 fatcat:hlkkabuhrzhkrmuyqomzfmc6zm

Multi-Threaded Processors [chapter]

David Padua, Amol Ghoting, John A. Gunnels, Mark S. Squillante, José Meseguer, James H. Cownie, Duncan Roweth, Sarita V. Adve, Hans J. Boehm, Sally A. McKee, Robert W. Wisniewski, George Karypis (+29 others)
2011 Encyclopedia of Parallel Computing  
Underutilization of a superscalar processor due to missing instruction-level parallelism can be overcome by simultaneous multithreading, where a processor can issue multiple instructions from multiple  ...  Simultaneous multithreaded processors combine the multithreading technique with a wideissue superscalar processor such that the full issue bandwidth is utilized by potentially issuing instructions from  ...  be followed (high confidence) or both continuations should be followed simultaneously (low confidence).  ... 
doi:10.1007/978-0-387-09766-4_423 fatcat:heb3n2cfwnbi5nvxv5kvxd2xgm

A Low-Power Multithreaded Processor for Baseband Communication Systems [chapter]

Michael Schulte, John Glossner, Suman Mamidi, Mayan Moudgill, Stamatis Vassiliadis
2004 Lecture Notes in Computer Science  
Furthermore, these processors should be compiler-friendly, so that code for them can quickly be developed in a high-level language.  ...  Embedded digital signal processors for baseband communication systems have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency.  ...  Conclusion This paper has presented the design of a high-performance, low-power processor for baseband communication systems.  ... 
doi:10.1007/978-3-540-27776-7_41 fatcat:tqe3lzqjorcepmx7eij2fhya2a

A survey of processors with explicit multithreading

Theo Ungerer, Borut Robič, Jurij Šilc
2003 ACM Computing Surveys  
Several multithreaded processors are announced by industry or already into production in the areas of high-performance microprocessors, media, and network processors.  ...  Simultaneous multithreaded processors combine the multithreading technique with a wide-issue superscalar processor to utilize a larger part of the issue bandwidth by issuing instructions from different  ...  ACKNOWLEDGMENTS The authors would like to thank anonymous reviewers for many valuable comments.  ... 
doi:10.1145/641865.641867 fatcat:u6x7jdmkfvexnm3culskjsoxwi

C-slow Technique vs Multiprocessor in designing Low Area Customized Instruction set Processor for Embedded Applications [article]

Muhammad Adeel Akram, Aamir Khan, Muhammad Masood Sarfaraz
2012 arXiv   pre-print
Primary requirement for consumer electronic industry is low cost with high performance and low power consumption.  ...  set extensible processor architecture and others require more number of processing units on a single chip like Thread Level Parallelism (TLP) that includes Simultaneous Multithreading (SMT), Chip Multithreading  ...  Simultaneous Multithreading (SMT) processors, in contrast to ILP allow multiple independent threads to issue multiple processing units.  ... 
arXiv:1204.1179v1 fatcat:i2v5ls2upbgxhewerxnmjquxty

Next Generation Embedded Processor Architecture for Personal Information Devices [chapter]

In-Pyo Hong, Yong-Joo Lee, Yong-Surk Lee
2006 Lecture Notes in Computer Science  
Among more enhanced processor types, out-of-order superscalar cannot be a candidate for embedded applications due to its excessive complexity and relatively low performance gain compared to its overhead  ...  Latest high performance embedded processors are developed to achieve high clock speed.  ...  Some embedded processors employ high performance out-oforder superscalar technique that induces large chip area and design complexity.  ... 
doi:10.1007/11802167_47 fatcat:t73s55vutnbjhmunmeqvtlb6wy

Improving latency tolerance of multithreading through decoupling

J.-M. Parcerisa, A. Gonzalez
2001 IEEE transactions on computers  
For the nondecoupled multithreaded processor, the loss of performance is about 23 percent.  ...  This work presents and evaluates a novel processor microarchitecture which combines two paradigms: simultaneous multithreading and access/execute decoupling.  ...  ACKNOWLEDGMENTS The authors thank the anonymous referees for their valuable comments.  ... 
doi:10.1109/12.956093 fatcat:id5zuvaajfcildot55nuokrb4m

The impact of out-of-order commit in coarse-grain, fine-grain and simultaneous multithreaded architectures

R. Ubal, J. Sahuquillo, S. Petit, P. Lopez, J. Duato
2008 Proceedings, International Parallel and Distributed Processing Symposium (IPDPS)  
Experimental results show that, for the same performance, out-of-order commit permits to reduce multithread hardware complexity (e.g., fine grain multithreading with a lower number of supported threads  ...  Multithreaded processors in their different organizations (simultaneous, coarse grain and fine grain) have been shown as effective architectures to reduce the issue waste.  ...  processor outperforms, on average, a simultaneous multithreaded ROBbased processor; (ii) a simultaneous multithreaded VBbased processor reaches the maximum performance with about half the number of hardware  ... 
doi:10.1109/ipdps.2008.4536284 dblp:conf/ipps/UbalSPLD08 fatcat:evycgvofdfaljoxaqsjhcqwnim

A multithreaded PowerPC processor for commercial servers

J. M. Borkenhagen, R. J. Eickemeyer, R. N. Kalla, S. R. Kunkel
2000 IBM Journal of Research and Development  
A multithreaded PowerPC processor for commercial servers This paper describes the microarchitecture of the RS64 IV, a multithreaded PowerPC ® processor, and its memory system.  ...  The most significant of these is the use of coarse-grained multithreading to enable the processor to perform useful instructions during cache misses.  ...  In order to achieve high processor performance with minimal complexity, it is important to keep the cache latencies as small as possible.  ... 
doi:10.1147/rd.446.0885 fatcat:6n35k2rsqvbpvigzujaizluw5a

A Low-Power Multithreaded Processor for Software Defined Radio

Michael Schulte, John Glossner, Sanjay Jinturkar, Mayan Moudgill, Suman Mamidi, Stamatis Vassiliadis
2006 Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology  
In this paper, we present the design of the Sandblaster Processor, a low-power multithreaded digital signal processor for software defined radio.  ...  Furthermore, due to rapidly evolving communication standards with increasing code complexity, these processors must be compiler-friendly, so that code for them can quickly be developed in a high-level  ...  In this paper, we present the Sandblaster Processor, a low-power multithreaded digital signal processor for SDR.  ... 
doi:10.1007/s11265-006-7267-1 fatcat:nfqhlyks6bhmnfyg2opfpsm4xy
« Previous Showing results 1 — 15 out of 2,189 results