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Supply-Scalable High-Speed I/O Interfaces
2020
Electronics
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However, there are many challenges to be addressed to facilitate the realization of a true sense of supply-scalable I/O. ...
Introducing supply voltage scalability is expected to significantly improve the energy efficiency of communication input/output (I/O) interfaces as well as make the I/Os efficiently adapt to actual utilization ...
Although current-mode logic (CML) circuits have been a majority for base circuit topology for high-speed I/O interfaces owing to their high-speed capability [46] , using CMOS circuits as much as possible ...
doi:10.3390/electronics9081315
fatcat:b4npjvjbz5gwxei5eaiwrjjvkm
A variable-frequency parallel I/O interface with adaptive power-supply regulation
2000
IEEE Journal of Solid-State Circuits
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This paper presents a low-power high-speed CMOS signaling interface that operates off of an adaptively regulated supply. ...
tracks with the I/O frequency to filter out high-frequency noise. ...
CONCLUSION To meet the challenges of potential performance bottlenecks and constraints in aggressively scaled chips, we proposed a low-power high-speed I/O interface. ...
doi:10.1109/4.881205
fatcat:2te32xf65naevnfsurqmtzckvu
Low-power area-efficient high-speed I/O circuit techniques
2000
IEEE Journal of Solid-State Circuits
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These circuit techniques enable a high level of I/O integration to relieve the pin bandwidth bottleneck of modern VLSI chips. ...
We present a 4-Gb/s I/O circuit that fits in 0.1-mm 2 of die area, dissipates 90 mW of power, and operates over 1 m of 7-mil 0.5-oz PCB trace in a 0.25-m CMOS technology. ...
Because of offset cancellation, the I/O circuits operate quite reliably with very small voltage swings. ...
doi:10.1109/4.881204
fatcat:pm26zhemlndbxnqczcfnlhguqi
A 27-mW 3.6-Gb/s I/O Transceiver
2004
IEEE Journal of Solid-State Circuits
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Index Terms-I/O, low power, transceiver. ...
This paper describes a 3.6-Gb/s 27-mW transceiver for chip-to-chip applications. A voltage-mode transmitter is proposed that equalizes the channel while maintaining impedance matching. ...
ACKNOWLEDGMENT The authors thank National Semiconductor for fabrication. ...
doi:10.1109/jssc.2004.825259
fatcat:sgzhbfrepvhgzgsfcyjddv2eei
Future Microprocessor Interfaces: Analysis, Design and Optimization
2007
2007 IEEE Custom Integrated Circuits Conference
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High-aggregate bandwidth interfaces with minimized power, silicon area, cost and complexity will be essential to the viability of future microprocessor systems. ...
Interconnect and circuit density improvements are identified as a promising research direction to maximize the bandwidth and power efficiency of future microprocessor platforms. ...
We also thank past members of CRL's Signaling Research for their many contributions. ...
doi:10.1109/cicc.2007.4405777
dblp:conf/cicc/CasperBJKM07
fatcat:yzwg3rnhfzh7ppe3gkfse6d5zy
Optical technology for energy efficient I/O in high performance computing
2010
IEEE Communications Magazine
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The presented near-term optical I/O uses a customized package to assemble CMOS integrated transceiver circuits, discrete VCSEL/detector arrays, and polymer waveguides. ...
Future high-performance computing systems will require optical I/O to achieve their aggressive bandwidth requirements of multiple terabytes per second with energy efficiency better than 1 pJ/b. ...
Equalization can cancel ISI and open the received data eye, but requires additional circuit complexity, which increases I/O power and area. ...
doi:10.1109/mcom.2010.5594695
fatcat:dxvxk6h64bf5hkvoepfqewyg4u
BladeCenter midplane and media interface card
2005
IBM Journal of Research and Development
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Since highspeed designs can easily result in higher implementation costs, a significant predesign simulation effort was undertaken to analyze and prioritize design guidelines in order to develop a high-speed ...
Also, to ensure that the architecture will be flexible enough to support multiple input/output fabric protocols, SerDes (serialized/deserialized) is used as the internal high-speed communication electrical ...
was used for this high-speed internal input/output (I/O) fabric. ...
doi:10.1147/rd.496.0823
fatcat:p5ih5efspjfyfn6wfzcpj2hcba
Equalization and near-end crosstalk (NEXT) noise cancellation for 20-Gb/s 4-PAM backplane serial I/O interconnections
2005
IEEE transactions on microwave theory and techniques
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BACKPLANE CHANNEL LOSS As high speed I/O interface technology evolves, resistive loss affects the link performance by decreasing the signal amplitude and slowing edge rates. ...
In most high-speed networking applications, sophisticated Input/Output (I/O) interfaces are used to transfer multi-Gbit/sec data streams between the control processors on each line card. ...
doi:10.1109/tmtt.2004.839311
fatcat:jhbnrnj5qzelbh5hkwwhq2bxxy
A 0.47–0.66 pJ/bit, 4.8–8 Gb/s I/O Transceiver in 65 nm CMOS
2013
IEEE Journal of Solid-State Circuits
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A low-power forwarded-clock I/O transceiver architecture is presented that employs a high degree of output/input multiplexing, supply-voltage scaling with data rate, and low-voltage circuit techniques ...
Fabricated in a general purpose 65nm CMOS process, the transceiver achieves 4.8-8Gb/s at 0.47-0.66pJ/b energy efficiency for V DD =0.6-0.8V. ...
Index Terms -High-speed I/O, low-power, voltage-mode driver, injection-locked oscillator, transceiver, low-voltage regulator, poly-phase filter INTRODUCTION Total I/O bandwidth demand is growing in high-performance ...
doi:10.1109/jssc.2013.2249812
fatcat:j4xwhhhdjrgupcchwpbhhdiczm
A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces
2007
2007 Asia and South Pacific Design Automation Conference
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For the first time, we implemented a reconfigurable load-balanced TDM switch IC with SERDES interface circuits for high speed networking applications. ...
The TDM switch IC contained a digital 8x8 TDM switch core with 8B10B CODECs and analog SERDES I/O interfaces. ...
The CML input interface consists of an equalizer, an inductive-peaking active feedback CML limiting amplifier and a DC offset canceling circuit. ...
doi:10.1109/aspdac.2007.357961
dblp:conf/aspdac/HsuKTCWH07
fatcat:tbdomd74w5b7nbvg6eiwoj652q
A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS
2009
2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers
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CONCLUSION A compact I/O with a power-efficient DFE-IIR receiver targeting high-speed serial I/O for dense silicon carrier links is reported. ...
His current research interests include high-speed I/O design, PLL design, and circuit/system approaches for variability compensation. 2031015 Fig. 1 . 20310151 Manuscript received April 27, 2009; revised ...
doi:10.1109/isscc.2009.4977368
dblp:conf/isscc/LiuKDBF09
fatcat:2v7rwkgtr5g4jp6bahtxoyw6im
A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS
2009
IEEE Journal of Solid-State Circuits
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A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is reported. ...
Based on expected channel characteristics, the proposed I/O features low-impedance transmitter termination, high-impedance receiver termination, and a receiver with modified DFE with IIR filter feedback ...
CONCLUSION A compact I/O with a power-efficient DFE-IIR receiver targeting high-speed serial I/O for dense silicon carrier links is reported. ...
doi:10.1109/jssc.2009.2031015
fatcat:kc52jf2gn5clzdchkgcalbopbq
Inter-Pin Skew Compensation Scheme for 3.2-Gb/s/pin Parallel Interface
2010
JSTS Journal of Semiconductor Technology and Science
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An inter-pin skew compensation scheme is proposed, which minimizes the inter-pin skew of parallel interface induced by unequal trace length and loading of printed circuit board (PCB). ...
The proposed scheme is applied to 3.2-Gb/s/pin DDR4 SDRAM and implemented in a 0.18 m CMOS process. ...
The additional hardware for inter-pin skew compensation is minimal because the circuit blocks for normal I/O operation are re-used. ...
doi:10.5573/jsts.2010.10.1.045
fatcat:5gujggiyg5dxlktucgtou6azeu
Holistic Die-to-Die Interface Design Methodology for 2.5D Multi-Chip-Module Systems
2021
IEEE Transactions on Components, Packaging, and Manufacturing Technology
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A detailed analysis of energy per bit relationship to the voltage swing requirement for different topologies is presented along with a specific CML signalling oriented design flow for 2.5D chip to chip ...
interfaces as an example of topology specific optimization possibilities within this methodology. ...
Balamurugan et al. modelled and statistically analysed high speed input-output (IO) links [4] . with various noise sources in entire link, obtaining a methodology for estimating the jitter and eye diagram ...
doi:10.1109/tcpmt.2021.3117118
fatcat:kwz3onpmqrb65ckziwxilkzhsq
A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications
2020
Advances in Science, Technology and Engineering Systems
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interfaces. ...
cables) and including the system-level characteristics of transmitter and receiver (voltage swing, impedance, etc.), computes the eye diagram and the bit-error rate that is obtained in high-speed serial ...
Luca Selmi (University of Modena and Reggio Emilia) for support. ...
doi:10.25046/aj050266
fatcat:pmjheosntvaznb5v5rz7n6z3sa
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