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A hyperplane based approach for optimizing spatial locality in loop nests

M. Kandemir, A. Choudhary, N. Shenoy, P. Banerjee, J. Ramanujam
1998 Proceedings of the 12th international conference on Supercomputing - ICS '98  
We discuss the cases where data transformations are preferable to loop transformations and show that under specific conditions a loop nest can be optimized for perfect spatial locality by using data transformations  ...  This paper presents a data layout optimization technique based on the theory of hyperplanes from linear algebra.  ...  an approach based on hyperplane theory and available linear algebra framework used by parallelizing compilers for optimizing memory layouts of arrays.  ... 
doi:10.1145/277830.277849 dblp:conf/ics/KandemirCSBR98 fatcat:kkjdke3v2be5hivqyquqlbg3jq

A Loop Transformation Algorithm Based on Explicit Data Layout Representation for Optimizing Locality [chapter]

M. Kandemir, J. Ramanujam, A. Choudhary, P. Banerjee
1999 Lecture Notes in Computer Science  
Such a capability is required for a global locality optimization framework that applies both loop and data transformations to a sequence of loop nests for optimizing locality.  ...  Our method finds a nonsingular iteration-space transformation matrix such that in a given loop nest spatial locality is exploited in the innermost loops where it is most useful.  ...  w = 1, N C[w,u] += A[w,v] * B[v,u] end do end do end do (c) Transformation for optimizing spatial locality Our objective is to transform a loop nest such that spatial locality will be exploited in the  ... 
doi:10.1007/3-540-48319-5_3 fatcat:mnxqjncxovc6pfub65vrenl7d4

A Matrix-Based Approach to Global Locality Optimization

Mahmut Kandemir, Alok Choudhary, J. Ramanujam, Prith Banerjee
1999 Journal of Parallel and Distributed Computing  
In our approach, the loop nests in a program are processed one by one and the data layout constraints obtained from one nest are propagated for the optimizing the remaining loop nests.  ...  Global locality optimization is a technique for improving the cache performance of a sequence of loop nests through a combination of loop and data layout transformations.  ...  Acknowledgments We wish to thank the anonymous referees for their insightful comments and suggestions.  ... 
doi:10.1006/jpdc.1999.1552 fatcat:kuchv6xffvbw3g5uzqw6wu56qu

A linear algebra framework for automatic determination of optimal data layouts

M. Kandemir, A. Choudhary, N. Shenoy, P. Banerjee, J. Ramenujarn
1999 IEEE Transactions on Parallel and Distributed Systems  
We discuss the cases where data transformations are preferable to loop transformations and show that under certain conditions a loop nest can be optimized for perfect spatial locality by using data transformations  ...  This paper presents a data layout optimization technique for sequential and parallel programs based on the theory of hyperplanes from linear algebra.  ...  ACKNOWLEDGMENTS A preliminary version of this paper appears in the Proceedings of the 1998 ACM International Conference on Supercomputing  ... 
doi:10.1109/71.752779 fatcat:m3pdemgp5banxeyqqzzndmfah4

A layout-conscious iteration space transformation technique

M. Kandemir, J. Ramanujam, A. Choudhary, P. Banerjee
2001 IEEE transactions on computers  
Such a capability is required for a global locality optimization framework that applies both loop and data transformations to a sequence of loop nests for optimizing locality.  ...  In addition, our approach can work in those cases where the data layouts of a subset of the referenced arrays is unknown; this is a key step in optimizing a sequence of loop nests and whole programs for  ...  TRANSFORMATIONS FOR THE SINGLE LAYOUT CASE Optimizing Spatial Locality Our goal is to transform a loop nest such that spatial locality will be exploited in the inner loops in the transformed nest.  ... 
doi:10.1109/tc.2001.970571 fatcat:2r5arlhhkzbazpfu3lfnmdthcy

Enhancing spatial locality via data layout optimizations [chapter]

M. Kandemir, A. Choudhary, J. Ramanujam, N. Shenoy, P. Banerjee
1998 Lecture Notes in Computer Science  
Since the iteration space based locality optimizations also change the spatial reuse vectors, our approach allows us to compare the iteration-space based and data-space based approaches in terms of their  ...  First, it allows us to develop an array restructuring framework based on a combination of hyperplane theory and reuse vectors.  ...  Related Work The compiler work in optimizing loop nests for locality can be divided into two groups: (1) iteration space based optimizations and (2) data layout optimizations.  ... 
doi:10.1007/bfb0057885 fatcat:3pt3c2i6zncdbf4ptqcrkquk7u

Reducing false sharing and improving spatial locality in a unified compilation framework

M. Kandemir, A. Choudhary, J. Ramanujam, P. Banerjee
2003 IEEE Transactions on Parallel and Distributed Systems  
Given the conflicting requirements, a compiler-based approach to this problem holds promise.  ...  On an eight-processor SGI/Cray Origin 2000 multiprocessor, our approach brings an additional 9 percent improvement over a powerful locality optimization technique that uses both loop and data transformations  ...  The material presented in this paper is based on research supported in part by the US National Science Foundation grants CCR-9357840 and CCR-9509143, and the Air Force Materials Command under contract  ... 
doi:10.1109/tpds.2003.1195407 fatcat:os4br76rkbfmphyja2uimnbuoa

Improving Locality in Out-of-Core Computations Using Data Layout Transformations [chapter]

M. Kandemir, A. Choudhary, J. Ramanujam
1998 Lecture Notes in Computer Science  
In order to alleviate this problem, we propose a data layout optimization in this paper.  ...  Experimental results provide evidence that our method is effective for out-of-core nests whose data sizes far exceed the size of memory. D. O'Hallaron (Ed.): LCR'98  ...  In order to explain the problem with loop transformation based techniques in detail, we consider loop permutation [7] , a well-known transformation to improve locality in loop nests.  ... 
doi:10.1007/3-540-49530-4_27 fatcat:oype4odzvbgsblqm2b4dusaeja

Effective automatic parallelization of stencil computations

Sriram Krishnamoorthy, Muthu Baskaran, Uday Bondhugula, J. Ramanujam, Atanas Rountev, P Sadayappan
2007 Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation - PLDI '07  
Compiler frameworks have also been developed that can transform sequential stencil codes for optimization of data locality and parallelism.  ...  In this paper, we develop an approach for automatic parallelization of stencil codes, that explicitly addresses the issue of load-balanced execution of tiles.  ...  We thank David Callahan for suggesting split tiling.  ... 
doi:10.1145/1250734.1250761 dblp:conf/pldi/KrishnamoorthyBBRRS07 fatcat:m3cyagrr2rdrlljligiphr53tm

Effective automatic parallelization of stencil computations

Sriram Krishnamoorthy, Muthu Baskaran, Uday Bondhugula, J. Ramanujam, Atanas Rountev, P Sadayappan
2007 SIGPLAN notices  
Compiler frameworks have also been developed that can transform sequential stencil codes for optimization of data locality and parallelism.  ...  In this paper, we develop an approach for automatic parallelization of stencil codes, that explicitly addresses the issue of load-balanced execution of tiles.  ...  We thank David Callahan for suggesting split tiling.  ... 
doi:10.1145/1273442.1250761 fatcat:xij5hgziqrh63lma6dl4izoxjy

A practical automatic polyhedral parallelizer and locality optimizer

Uday Bondhugula, Albert Hartono, J. Ramanujam, P. Sadayappan
2008 SIGPLAN notices  
The system also enables the easy use of powerful empirical/iterative optimization for general arbitrarily nested loop sequences.  ...  We present the design and implementation of an automatic polyhedral source-to-source transformation framework that can optimize regular programs (sequences of possibly imperfectly nested loops) for parallelism  ...  In addition, we thank Alain Darte for useful feedback that has helped us improve the presentation. This work was supported in part by the U.S.  ... 
doi:10.1145/1379022.1375595 fatcat:mx5tqjwvdzfelgf4j7rrwb7ojm

A practical automatic polyhedral parallelizer and locality optimizer

Uday Bondhugula, Albert Hartono, J. Ramanujam, P. Sadayappan
2008 Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation - PLDI '08  
The system also enables the easy use of powerful empirical/iterative optimization for general arbitrarily nested loop sequences.  ...  We present the design and implementation of an automatic polyhedral source-to-source transformation framework that can optimize regular programs (sequences of possibly imperfectly nested loops) for parallelism  ...  In addition, we thank Alain Darte for useful feedback that has helped us improve the presentation. This work was supported in part by the U.S.  ... 
doi:10.1145/1375581.1375595 dblp:conf/pldi/BondhugulaHRS08 fatcat:oxeykavud5fqffeswz3o7k5ote

Effective automatic computation placement and dataallocation for parallelization of regular programs

Chandan Reddy, Uday Bondhugula
2014 Proceedings of the 28th ACM international conference on Supercomputing - ICS '14  
However, these recent approaches used a simple strategy to map computation to nodestypically block or block-cyclic. These mappings may lead to excess communication volume for multiple loop nests.  ...  This paper proposes techniques for data allocation and computation mapping when compiling affine loop nest sequences for distributedmemory clusters.  ...  Acknowledgments This work was supported in part by a research gift from AMD. We would also like to acknowledge the Department of Science and Technology, India for a grant under the FIST program.  ... 
doi:10.1145/2597652.2597673 dblp:conf/ics/ReddyB14 fatcat:56ct6skdwrdr7apbp55du5zjnu

Parameterized Diamond Tiling for Stencil Computations with Chapel parallel iterators

Ian J. Bertolacci, Catherine Olschanowsky, Ben Harshbarger, Bradford L. Chamberlain, David G. Wonnacott, Michelle Mills Strout
2015 Proceedings of the 29th ACM on International Conference on Supercomputing - ICS '15  
Such techniques are difficult to include in general purpose optimizing compilers because of the need for inter-procedural pointer and array data-flow analysis, plus the need to tune scheduling strategies  ...  We show how such iterators can be used by programmers in stencil computations with multiple spatial dimensions.  ...  Loop tiling [17] changes the execution order of the iterations of a loop nest to improve data locality, which in turn reduces memory bandwidth pressure.  ... 
doi:10.1145/2751205.2751226 dblp:conf/ics/BertolacciOHCWS15 fatcat:r6gsrx4f3jax3egcdg3aepyqwu

Loop transformations for interface-based hierarchies IN SDF graphs

Jonathan Piat, Shuvra S. Bhattacharyya, Michael Raulet
2010 ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors  
This paper presents a systematic method for applying an important class of loop transformation techniques in the context of interface-based SDF semantics.The resulting approach provides novel capabilities  ...  A new type of hierarchy (Interface-based SDF) has been proposed allowing more expressivity while maintaining its predictability.  ...  the author introduces a nested loops optimization technique which aims at transforming a nested loop in a nested loop for which some (all in the optimal case) of the internal loops can be computed in parallel  ... 
doi:10.1109/asap.2010.5540954 dblp:conf/asap/PiatBR10 fatcat:tsga6jyvvbgdveskwbxyabmt6u
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