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Application-specific Processor Architecture: Then and Now

Peter Cappello
2007 Journal of Signal Processing Systems  
In sum, application performance requirements that justify a special-purpose architecture often require parallelism: (1) Sufficiently high performance implies parallelism.  ...  We describe a 2D architectural taxonomy, identifying what, we believe, to be a Bsweet spot^for architectural research.  ...  Although not shown, the SDRAM is distributed among the TRIPS chips. So, there is an interleaving of memory and processors, albeit across chips.  ... 
doi:10.1007/s11265-007-0127-9 fatcat:dmcbpubj2rdajplt2j6sqcjmxu

High-performance DSP architectures for intelligence and control applications

1991 IEEE Control Systems  
High-precision control and fault-tolerance are achieved by exploiting the high-speed arithmetic, on-chip peripherals, direct memory access (DMA) controllers, multiprocessor support and bitmanipulation  ...  This paper describes the architectural features of DSPs for intelligence and control applications, and the node configuration of the IX-n generalpurpose neurocomputer, based on the commercially available  ...  Acknowledgment The authors gratefully acknowledge the help of Rosemary Mattingley, and the support of the Department of Electrical and Computer Engineering, Drexel University and the Faculty of Electrical  ... 
doi:10.1109/37.88592 fatcat:vhs764wo7vghvphh2gfkv3chka

Exploring hardware support for scaling irregular applications on multi-node multi-core architectures

Simone Secchi, Marco Ceriani, Antonino Tumeo, Oreste Villa, Gianluca Palermo, Luigi Raffo
2013 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors  
This paper presents a multi-node, multi-core, multi-threaded shared-memory system architecture designed for the execution of large-scale irregular applications, and built on top of three pillars that support  ...  An analytical performance model that accounts for the main architecture and application characteristics is presented.  ...  In this paper, we present the design of a new full-system architecture for irregular applications based on commodity processors.  ... 
doi:10.1109/asap.2013.6567595 dblp:conf/asap/SecchiCTVPR13 fatcat:ynu4zfwjtratdlow4pzumvb2em

Coarse-Grained Reconfigurable Array: Architecture and Application Mapping

Kiyoung Choi
2011 IPSJ Transactions on System LSI Design Methodology  
It is a current trend to integrate multiple cores on a chip to alleviate such problem, but software only implementation is not yet a solution for high-end embedded systems.  ...  The cenral memory is divided into several smaller memory blocks, with each part connected to its own master (processor, PE array, network/bus interface are masters).  ...  His primary interests include various aspects of computer-aided electronic systems design including embedded systems design, high-level synthesis, and low-power systems design.  ... 
doi:10.2197/ipsjtsldm.4.31 fatcat:46ph7de3wreexmn6wl3ealzzhy

Review of recent trends in Coarse Grain Reconfigurable Architectures for signal processing applications

Sridharan M.., R. Ramya
2018 Advances in Systems Science and Applications  
The research shows that the coarse grain reconfigurable architectures with heterogeneous processing elements are a better option for system design in DSP applications which exploit granularity matching  ...  between the algorithms and the processing hardware, and also the inherent parallelism of DSP algorithms for the realization of low power DSP systems.  ...  The architecture relies on high bandwidth, distributed memory integrated in 3D within the logic tile.  ... 
doi:10.25728/assa.2018.18.1.508 fatcat:eihxjjbe5fbtfidecoa4j7sv6y

Survey on Near-Data Processing: Applications and Architectures

Paulo Cesar Santos, Francis Birck Moreira, Aline Santana Cordeiro, Sairo Raoní Santos, Tiago Rodrigo Kepe, Luigi Carro, Marco Antonio Zanata Alves
2021 Journal of Integrated Circuits and Systems  
One of the main challenges for modern processors is the data transfer between processor and memory. Such data movement implies high latency and high energy consumption.  ...  This survey presents a brief history of these accelerators, focusing on the applications domains migrated to near-data and the proposed architectures.  ...  ACKNOWLEDGEMENTS This work was partially supported by FAPERGS, CAPES, CNPq and Serrapilheira Institute (grant number Serra-1709-16621).  ... 
doi:10.29292/jics.v16i2.502 fatcat:3uiswd6z65djpjgvsxclutthxu

Windowed FIFOs for FPGA-based Multiprocessor Systems

Kai Huang, David Grunert, Lothar Thiele
2007 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)  
FPGA-based multiprocessor systems are viable solutions for stream-based embedded applications. They provide a software abstraction which enables coarse-grained parallel deployment on an FPGA chip.  ...  A widely used model for such a deployment is the class of Kahn process networks despite their limitation to pure FIFO communications.  ...  Although the KPN architecture offers distributed control and a simple interface for programming, it also has limitations that make the implementation of stream-based applications difficult or inefficient  ... 
doi:10.1109/asap.2007.4429955 dblp:conf/asap/HuangGT07 fatcat:c6jgf6kq5nboxim7vjs2wrpc3i

The Impact of Thread-Per-Core Architecture on Application Tail Latency

Pekka Enberg, Ashwin Rao, Sasu Tarkoma
2019 2019 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS)  
We measure the impact of thread-per-core architecture on application tail latency by implementing a key-value store that uses application-level partitioning, and inter-thread messaging and compare its  ...  The thread-per-core architecture has emerged to reduce these overheads, but it also has its challenges from thread synchronization and OS interfaces.  ...  ACKNOWLEDGMENTS We would like to thank the anonymous reviewers for their feedback, and Lirim Osmani for helping us setup the experimental evaluation testbed.  ... 
doi:10.1109/ancs.2019.8901874 dblp:conf/ancs/EnbergRT19 fatcat:562bidsjpjeobfhwfqheqrmp2a

A Triplet-based Computer Architecture Supporting Parallel Object Computing

Feng Shi, Weixing Ji, Baojun Qiao, Bin Liu, Haroon-ul-Rashid
2007 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)  
A distributed deterministic routing algorithm (DDRA) is elaborated, already proposed for THIN.  ...  TriBA achieves the unification of software architecture and computer, and also relieves the burden of parallel programming.  ...  Interconnection network THIN offers a high degree of regularity, scalability, and symmetry, which very well conforms to a modular design and implementation of distributed systems involving a large number  ... 
doi:10.1109/asap.2007.4429979 dblp:conf/asap/ShiJQLH07 fatcat:sy2dbtirxvhadjzsxkqrswizru

An MPSoC architecture for the Multiple Target Tracking application in driver assistant system

Jehangir Khan, Smail Niar, Atika Menhaj, Yassin Elhillali, Jean Luc Dekeyser
2008 2008 International Conference on Application-Specific Systems, Architectures and Processors  
In our implementation of MTT, several independent parallel tasks have been identified and mapped onto a multiprocessor architecture to ensure the deadlines imposed by the application.  ...  Our study demonstrates that the joint utilization of reconfigurable circuits (namely FPGA) and MPSoC, facilitates the development of a flexible and efficient MTT system.  ...  Dedicated hardware implementation may be useful for high speed processing but it does not offer the flexibility and programmability required for system evolution.  ... 
doi:10.1109/asap.2008.4580166 dblp:conf/asap/KhanNRED08 fatcat:rjbb2omzufhczixyrykqvft37q

ASAM: Automatic Architecture Synthesis and Application Mapping

Lech Jozwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri (+1 others)
2012 2012 15th Euromicro Conference on Digital System Design  
.  Abstract -This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable applicationspecific instruction-set  ...  Index Terms-embedded systems, heterogeneous multiprocessor system-on-chip (MPSoC), customizable ASIPs, architecture synthesis, MPSoC and ASIP design automation;  ...  on major physical system characteristics (area, speed, energy consumption); -substantially decreasing the high system development and production costs, and long development times.  ... 
doi:10.1109/dsd.2012.28 dblp:conf/dsd/JozwiakLCMMMDGJPPTR12 fatcat:et5s2vcnhzbfrae2jufsqzq4gy

Architecture and applications of the Connection Machine

L.W. Tucker, G.G. Robertson
1988 Computer  
Demands for faster and larger computer systems increase steadily.  ...  The first uses exotic technology in a fairly conventional serial computer architecture. This approach suffers from manufacturing and maintenance problems and high costs.  ...  Finally, the designers wanted the CM-2 to incorporate a high-speed I/O system for peripheral data storage and display devices.  ... 
doi:10.1109/2.74 fatcat:zog5vvidhba3rn6p2tsco52o54

Rationale and Architecture Principles for Medical Application Platforms

John Hatcliff, Andrew King, Insup Lee, Alasdair Macdonald, Anura Fernando, Michael Robkin, Eugene Vasserman, Sandy Weininger, Julian M. Goldman
2012 2012 IEEE/ACM Third International Conference on Cyber-Physical Systems  
However, a vision is emerging of a notion of a medical application platform (MAP) that would provide device and health information systems (HIS) interoperability, safety critical network middleware, and  ...  The concept of "system of systems" architecture is increasingly prevalent in many critical domains.  ...  ACKNOWLEDGEMENTS The authors gratefully acknowledge discussions with the Medical Device Safety and Interoperability Working Group and NIBIB Quantum Project "Development of a Prototype Healthcare Intranet  ... 
doi:10.1109/iccps.2012.9 dblp:conf/iccps/HatcliffKLMFRVWG12 fatcat:hhfwc4zhpnhj5l3y2jna5xeemi

Fog Computing: principles, architectures, and applications [chapter]

A.V. Dastjerdi, H. Gupta, R.N. Calheiros, S.K. Ghosh, R. Buyya
2016 Internet of Things  
In addition, a reference architecture for Fog computing is presented and recent related development and applications are discussed.  ...  Fog computing is a paradigm for managing a highly distributed and possibly virtualized environment that provides compute and network services between sensors and cloud data centers.  ...  The proposed system achieves a high sensitivity and specificity when tested against real-world data.  ... 
doi:10.1016/b978-0-12-805395-9.00004-6 fatcat:l3flj4am7rhl5pidoujsulhzfi

Transputer systems for the Macintosh

1988 Proceedings of the third conference on Hypercube concurrent computers and applications Architecture, software, computer systems, and general issues -  
The Transptier (transistor-computer) is a 32-bit high speed reduced instruction set computer (RISC), based on VLSI technology, and designed for parallel processing applications. lt is manufactured by lnmos  ...  If there is one in the system, the processor type, memory size, speed, and number of processors can be determined.  ... 
doi:10.1145/62297.62421 fatcat:rbbpglsajfdcdmmjmaadxcbnde
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