34,094 Hits in 2.9 sec


Azalia Mirhoseini, Anna Goldie, Hieu Pham, Benoit Steiner, Quoc Le, Jeff Dean
We introduce a hierarchical model for efficient placement of computational graphs onto hardware devices, especially in heterogeneous environments with a mixture of CPUs, GPUs, and other computational devices  ...  Experiments with widely-used computer vision and natural language models show that our algorithm can find optimized, non-trivial placements for TensorFlow computational graphs with over 80,000 operations  ...  Figure 1 : 1 Hierarchical model for device placement (see text for more details). • ResNet (He et al., 2016 ) is a popular model for image classification.  ... 

Analog layout synthesis - Recent advances in topological approaches

H. Graeb, F. Balasa, R. Castro-Lopez, Y.-W. Chang, F.V. Fernandez, P.-H. Lin, M. Strasser
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
The core issue in these approaches is the modeling of layout constraints for an efficient exploration process.  ...  This includes fast checking of constraint compliance, reducing the search space, and quickly relating topological encodings to placements.  ...  device model or a certain circuit functionality.  ... 
doi:10.1109/date.2009.5090670 fatcat:ex7apa6gdrfzbonrgronrf5ldi

GDP: Generalized Device Placement for Dataflow Graphs [article]

Yanqi Zhou, Sudip Roy, Amirali Abdolrashidi, Daniel Wong, Peter C. Ma, Qiumin Xu, Ming Zhong, Hanxiao Liu, Anna Goldie, Azalia Mirhoseini, James Laudon
2019 arXiv   pre-print
With increasingly complex neural network architectures and heterogeneous device characteristics, finding a reasonable placement is extremely challenging even for domain experts.  ...  Runtime and scalability of large neural networks can be significantly affected by the placement of operations in their dataflow graphs on suitable devices.  ...  For improved scalability, a hierarchical device placement strategy (HDP) (Mirhoseini et al., 2018) has been proposed that clusters operations into groups before placing the operation groups onto devices  ... 
arXiv:1910.01578v1 fatcat:d34thanfdbbhde5vajyef72j2e

A Distributed Application Placement and Migration Management Techniques for Edge and Fog Computing Environments [article]

Mohammad Goudarzi, Marimuthu Palaniswami, Rajkumar Buyya
2021 arXiv   pre-print
In this article, we propose a new weighted cost model for hierarchical fog computing environments, in terms of the response time of IoT applications and energy consumption of IoT devices, to minimize the  ...  Fog/Edge computing model allows harnessing of resources in the proximity of the Internet of Things (IoT) devices to support various types of real-time IoT applications.  ...  • We propose a new weighted cost model based on IoT applications' response time and IoT devices' energy consumption for application placement and migration of IoT devices in hierarchical fog/edge computing  ... 
arXiv:2108.02328v1 fatcat:sym3xyqzmncfla2deokpddop3e

Microservices-based IoT Application Placement within Heterogeneous and Resource Constrained Fog Computing Environments

Samodha Pallewatta, Vassilis Kostakos, Rajkumar Buyya
2019 Proceedings of the 12th IEEE/ACM International Conference on Utility and Cloud Computing - UCC'19  
In this paper, we propose a decentralized microservices-based IoT application placement policy for heterogeneous and resource constrained Fog environments.  ...  of Fog devices.  ...  ACKNOWLEDGMENTS We thank Redowan Mahmud, Mohammad Goudarzi and anonymous reviewers for their valuable comments and suggestions on improving this paper.  ... 
doi:10.1145/3344341.3368800 dblp:conf/ucc/PallewattaKB19 fatcat:mqr7lkhqyrb6tlq246rztyrprq

Multi-million gate FPGA physical design challenges

Maogang Wang, A. Ranjan, S. Raje
2003 ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)  
The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA.  ...  Hierarchical approaches to divide and conquer the design, early estimation tools for design exploration, and physical optimizations are some of the key methodologies that have to be introduced in the FPGA  ...  To motivate our argument for a discrete delay model, it would help to give an overview of routing architecture in Xilinx Virtex-II devices, details of which can be found in [28] .  ... 
doi:10.1109/iccad.2003.159780 fatcat:h66lt6ffijhoneb5xx4q6e7hri

Wireless Device-to-Device Caching Networks with Distributed MIMO and Hierarchical Cooperations

Jiajia Guo, Jinhong Yuan, Jian A. Zhang
2017 GLOBECOM 2017 - 2017 IEEE Global Communications Conference  
In this paper, we propose a new caching scheme for a random wireless device-to-device (D2D) network of nodes with local caches, where each node intends to download files from a prefixed library via D2D  ...  They showed that for a single-hop cache network, with an optimized caching placement strategy and cluster size, the network throughput scales as Θ ( ) , growing linearly with the size of local √ ) hierarchical  ...  We then obtain the following lemma. 1 Lemma 1: Under the channel model described in (12), applying the transmit power control in (16), a long-distance The optimal number of hierarchical stages for maximizing  ... 
doi:10.1109/glocom.2017.8254145 dblp:conf/globecom/GuoYZ17 fatcat:wzg5ohatuvhv7gp4r4t5oaj5sm

Calibration of Rent's rule models for three-dimensional integrated circuits

S. Das, A.P. Chandrakasan, R. Reif
2004 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Utilizing this model, we calculate the wiring requirement for a set of benchmark standard-cell circuits.  ...  We find that the Rahman model predicts wirelengths accurately (to within 20% of placement and of routing, on average), and suggest some areas for minor improvement to the model.  ...  ACKNOWLEDGMENT The authors would like to thank A. Rahman for helpful discussions and clarifications of the interconnect model used in this paper.  ... 
doi:10.1109/tvlsi.2004.825833 fatcat:zz2ynhbmobeyllcjwptg23w4oy

Wield: Systematic Reinforcement Learning With Progressive Randomization [article]

Michael Schaarschmidt, Kai Fricke, Eiko Yoneki
2019 arXiv   pre-print
We present Wield, a first-of-its kind system to facilitate task design for practical reinforcement learning.  ...  To guide experimentation, Wield further introduces a novel task design protocol and classification scheme centred around staged randomization to incrementally evaluate model capabilities.  ...  ACKNOWLEDGMENTS Michael Schaarschmidt is supported by a Google PhD Fellowship. We are also grateful for receiving research credits from Google Cloud.  ... 
arXiv:1909.06844v1 fatcat:hsaisvqntzex7ihfxzmhhmfalm

State-of-the-Art on Analog Layout Automation [chapter]

Ricardo Martins, Nuno Lourenço, Nuno Horta
2016 Analog Integrated Circuit Design Automation  
The chapter starts by addressing the placement problem in EDA, providing a brief overview of the most recent placement tools developed, followed by the presentation of the main references of automatic  ...  Finally, the available commercial solutions for analog layout automation are outlined.  ...  For a uniform random number of design points, layout samples are generated by a procedural layout generator and device parasitics are modeled by linear regression.  ... 
doi:10.1007/978-3-319-34060-9_2 fatcat:7flyp6nwd5aprexg2ccab4abau

State of the Art on Analog Layout Automation [chapter]

Ricardo M. F. Martins, Nuno C. C. Lourenço, Nuno C. G. Horta
2012 SpringerBriefs in Applied Sciences and Technology  
The chapter starts by addressing the placement problem in EDA, providing a brief overview of the most recent placement tools developed, followed by the presentation of the main references of automatic  ...  Finally, the available commercial solutions for analog layout automation are outlined.  ...  For a uniform random number of design points, layout samples are generated by a procedural layout generator and device parasitics are modeled by linear regression.  ... 
doi:10.1007/978-3-642-33146-6_2 fatcat:miizfmqdqbd67azo7hb3j72xna

An Analysis of Fog Computing Data Placement Algorithms

Daniel Maniglia Amancio da Silva, Godwin Asamooning, Hector Orrillo, Rute C. Sofia, Paulo M. Mendes
2020 arXiv   pre-print
Resultsachieved show that edge placement strategies are beneficial toassist cloud computing in lowering latency and cloud energyexpenditure.  ...  Fog devices model Fog nodes, i.e., devices capable of hosting application modules. Resource management is a core component of IFogSim and is composed by Placement and Scheduler.  ...  Application 1 corresponds to a low intensity application model. This can be, for instance, data periodically sent by environmental sensors to devices around (Fog and Cloud).  ... 
arXiv:2005.11847v1 fatcat:s7pi2z62nvg5zbrljs6wmvubbu

Smartphone-Based Activity Recognition in a Pedestrian Navigation Context

Robert Jackermeier, Bernd Ludwig
2021 Sensors  
In smartphone-based pedestrian navigation systems, detailed knowledge about user activity and device placement is a key information.  ...  We first collect a dataset of 28 combinations of device placements and activities, in total consisting of over 6 h of data from three sensors.  ...  The hierarchical approach proved advantageous especially in the cases where one of lower-level classifiers for a specific device placement greatly outperforms its generic counterpart, e.g., the dedicated  ... 
doi:10.3390/s21093243 pmid:34067137 pmcid:PMC8124139 fatcat:7m2deoar2nethg3ttaqpnr5zdm

Cooperative-hierarchical based edge-computing approach for resources allocation of distributed mobile and IoT applications

Maha Aljarah, Mohammad Shurman, Sharhabeel Alnabelsi
2020 International Journal of Electrical and Computer Engineering (IJECE)  
To validate our proposed cooperative-hierarchical approach for modules placement between edge nodes' resources, iFogSim toolkit is used.  ...  In this paper, exploiting edge resources is studied; therefore, a cooperative-hierarchical approach for executing the pre-partitioned applications' modules between edges resources is proposed, in order  ...  The configurations and characteristics for devices in both developed platforms are unified, in order to fairly compare our proposed cooperative-hierarchical modules placement method to the baseline placement  ... 
doi:10.11591/ijece.v10i1.pp296-307 fatcat:p3eg4ktohvfyvmj4k73gznhkl4

Hierarchical Placement with Layout Constraints [chapter]

Mark Po-Hung Lin, Yao-Wen Chang
2010 Analog Layout Synthesis  
This chapter first introduces the hierarchical constraints induced by circuit and layout design hierarchies, and then presents a hierarchical placement approach to better consider these hierarchical constraints  ...  In addition to these basic placement constraints, there exist hierarchical symmetry and hierarchical proximity constraints due to circuit and layout design hierarchies.  ...  The proximity constraint is widely used in the subcircuit of a common device model or a certain circuit functionality.  ... 
doi:10.1007/978-1-4419-6932-3_2 fatcat:enclmtlcy5al5bie2w3x5qgrpa
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