2,127 Hits in 7.5 sec

A scarce-state-transition Viterbi-decoder VLSI for bit error correction

T. Ishitani, K. Tansho, N. Miyahara, S. Kubota, S. Kato
1987 IEEE Journal of Solid-State Circuits  
In addition, three-layer metallization and an advanced hierarchical macroeell design method (HMC~have been adopted to improve packing density and reduce chip size.  ...  A high-speed Viterbi decoder VLSI with coding rate R = 1/2 and constraint length K = 7 for bit error correction has been developed using 1.5-pm n-well CMOS technology.  ...  SST VITERBI DECODER A. Function of SST Viterbi Decoder Reduction in hardware size and power dissipation was necessary to develop a single-chip Viterbi-decoder VLSI.  ... 
doi:10.1109/jssc.1987.1052775 fatcat:a3dnpir4yffllddgqzck7qxlry

Contrasts in Physical Design between LSI and VLSI

W.R. Heller
1981 18th Design Automation Conference  
With all this growth, a l t e r n a t i v e s in VLSI design style as well as packaging have to be considered.  ...  In the last five years, there has been rapid growth in logic and memory chip circuit density.  ...  If a "top-down" approach to a hierarchical structure is adapted in VLSI, we can see that the I/O pins of the substructure should be assigned for the benefit of the higher level, as one progresses down  ... 
doi:10.1109/dac.1981.1585426 fatcat:7wu2j5ur3ncizenzbjekbibvz4

Voltage drop reduction for on-chip power delivery considering leakage current variations

Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan
2007 2007 25th International Conference on Computer Design  
In this paper, we propose a novel on-chip voltage drop reduction technique for on-chip power delivery networks of VLSI systems in the presence of variational leakage current sources.  ...  Different from existing power grid noise reduction methods, the new approach considers the impacts of inter-die and intra-die variational leakage current sources due to unavoidable process variability  ...  Conclusions In this paper, we have proposed a fast statistical decap optimization algorithm for noise reduction of on-chip VLSI power delivery systems.  ... 
doi:10.1109/iccd.2007.4601883 dblp:conf/iccd/FanMT07 fatcat:ob5e6v77c5cl5jnx2wc5ophkam

A Strategy to Accelerate VLSI Various Leveled Physical Structure in Floor Planning

Karthick S
2019 Zenodo  
In this study, we have presented an effective model for brisk floor planning in VLSI top-down various leveled physical structure stream utilizing the active-logic reduction technology.  ...  With the fast increment in size and unpredictability of VLSI, it is difficult to meet speed and quality necessity of IC physical structure.  ...  CONCLUSION With the fast increment in size and unpredictability of VLSI, EDA apparatuses are utilized in progressively successful approach to meet speed and quality necessity of IC chip plan.  ... 
doi:10.5281/zenodo.2649813 fatcat:2xqvdey4nzbu3bzy3wh3kfpz7a

Simulation of Electrical and Optical Interconnections for Future VLSI ICs [chapter]

Grzegorz Tosik, Zbigniew Lisik, Malgorzata Langer, Frederic Gaffiot, Ian O'Conor
2004 Lecture Notes in Computer Science  
At present, metallic interconnections become the "bottleneck" of the further progress in VLSI technology.  ...  The clock distribution network (CDN) that is the most representative component of the modern VLSI circuits has been used as the test circuit and its numerical models for H-tree architecture have been worked  ...  The H-tree topology Transmission Line Model The interconnection system in a VLSI chip covers two power lines and one signal line as shown in Fig.4 .  ... 
doi:10.1007/978-3-540-25944-2_134 fatcat:d4xfwm5ftvaa3bdwro2zb4nr6u

Workshop Report: VLSI: Machine Architecture and Very High Level Languages

P. C. Treleaven
1982 Computer journal  
Ideas of hierarchical design, with a structured, modular approach to the problem have been adopted generally successfully in this area, and point the way ahead for VLSI designers.  ...  Gerry Sussman of the Massachusetts Institute of Technology then graphically illustrated the power of Mead and Conway VLSI design techniques by describing how they designed and implemented a LISP chip in  ... 
doi:10.1093/comjnl/25.1.153 fatcat:s5inqwp4ava7lhcpzkzfaj44oi

Large scale P/G grid transient simulation using hierarchical relaxed approach

Yici Cai, Jin Shi, Zhu Pan, Xianlong Hong, Sheldon X.-D. Tan
2008 Integration  
This paper proposes a hierarchical relaxed approach to analyze large scale on-chip power/ground (P/G) grids with C4 packages efficiently.  ...  Different from the existing hierarchical approach where macro models and time-consuming matrix density reduction technique are used, this novel approach uses an iterative relaxation procedure to explicitly  ...  On the other hand, node reduction-based approaches [9, 10] can be viewed as special hierarchical method.  ... 
doi:10.1016/j.vlsi.2007.04.003 fatcat:2kqvha2oync3jgk2l3yzyqn2fq

Design and Verification for Hierarchical Power Efficiency System (HPES) Design Techniques Using Low Power CMOS Digital Logic [chapter]

Taikyeong Jeong, Jaemyoung Lee
2006 Lecture Notes in Computer Science  
Our approach to designing reliable hardware involves techniques for hierarchical power efficiency system (HPES) design and a judicious mixture of verification method is verified by this formal refinement  ...  It also describes a new HPES integration method combining low power circuit for special purpose computers.  ...  For complex VLSI chips and systems, these 3 power reduction steps are dominant in terms of delay, power consumption and silicon area.  ... 
doi:10.1007/11758501_101 fatcat:uktamih2izghnigbypd5xt6v2i

PIM lite

Shyamkumar Thoziyoor, Jay Brockman, Daniel Rinzler
2005 Proceedings of the 15th ACM Great Lakes symposium on VLSI - GLSVSLI '05  
PIM Lite is a processor-in-memory prototype implemented in a 0.18 micron logic process.  ...  Minimizing processor state by keeping thread state in memory and using a regular, tiled and memory-centric design greatly simplified VLSI development and testing.  ...  verification of the VHDL model of PIM Lite, we followed a simple hierarchical bottom-top approach that served us well in verifying the functionality of different entities existing at different stages  ... 
doi:10.1145/1057661.1057678 dblp:conf/glvlsi/ThoziyoorBR05 fatcat:4stcg6dg55cj5hyauxaucskwyi

Computationally efficient locality-aware interconnection topology for multi-processor system-on-chip (MP-SoC)

Haroon-Ur-Rashid Khan, Feng Shi, WeiXing Ji, YuJin Gao, YiZhuo Wang, CaiXia Liu, Ning Deng, JiaXin Li
2010 Chinese Science Bulletin  
This paper evaluates the Triplet Based Architecture, TriBAa new idea in chip multiprocessor architectures and a class of Direct Interconnection Network (DIN).  ...  Computationally efficient locality-aware interconnection topology for multi-processor system-on-chip (MP-SoC).  ...  Tiled layout for TriBA Each of the nodes in TriBA is designed as a tile using Tiled Architecture approach so that no link is longer than the length or width of a tile.  ... 
doi:10.1007/s11434-010-4118-z fatcat:anzn23bafnchjd2a7n64ynfqce


Kim Ho Yeap, Kang Wei Thee, Koon Chun Lai, Humaira Nisar, K. Chandrasekaran Krishnan
2018 International Journal of Technology  
We show that our new design is capable of operating at 150 MHz (i.e., 12.5 times faster than the original design), with a significant reduction in chip size (i.e., the total area is 77249.814850 µm 2 )  ...  The power consumption of the chip is 593.9899 µW, which is at least 32% lower than that of other 8051 derivatives.  ...  The significant reduction in the effective channel length allows for an increase in the switching speed of the logic components (Sung et al., 1998) and less power required to turn on the transistors.  ... 
doi:10.14716/ijtech.v9i1.798 fatcat:yismwbnqjra3hbef3gjx3ktuqi

Efficient cell-based migration of VLSI layout

Eugene Shaphir, Ron Y. Pinter, Shmuel Wimer
2014 Optimization and Engineering  
In Intel's "Tick-Tock" roadmap a new processor is first manufactured in the most advanced stable process technology, followed in a 1-year delay by introducing chips comprising same microarchitecture but  ...  We describe a hierarchy-driven computationally efficient algorithm for cell-based layout conversion, used by Intel in its Tick-Tock roadmap.  ...  Acknowledgments The authors are thankful to Intel Corporation for supporting this work. They are also thankful for the useful reviewers' comments, which helped improving the manuscript.  ... 
doi:10.1007/s11081-014-9257-7 fatcat:j5zmr6ri4na4tguwe2qf6olv7u

Real-time stereo matching architecture based on 2D MRF model: a memory-efficient systolic array

Sungchan Park, Chao Chen, Hong Jeong, Sang Hyun Han
2011 EURASIP Journal on Image and Video Processing  
There is a growing need in computer vision applications for stereopsis, requiring not only accurate distance but also fast and compact physical implementation.  ...  If we expand it into N's multiple chips in a cascaded manner, we can cope with various ranges of image resolutions. We have realized it using the FPGA technology.  ...  Acknowledgements This work was supported by the following funds: the Brain Korea 21 project and the Ministry of Knowledge Economy, Korea, under the Core Technology Development for Breakthrough of Robot  ... 
doi:10.1186/1687-5281-2011-4 fatcat:m2qojiricfg7nltfhux5krqy2e

The VLSI High-Level Synthesis for Building Onboard Spacecraft Control Systems [chapter]

O. V. Nepomnyashchiy, I. V. Ryjenko, V. V. Shaydurov, N. Y. Sirotinina, A. I. Postnikov
2017 Proceedings of the Scientific-Practical Conference "Research and Development - 2016"  
In this paper, we propose a new approach to VLSI high-level synthesis based on a functional-flow parallel computing model.  ...  Further, this technology is suggested for use in the synthesis of onboard control system components for small spacecrafts. O.V. Nepomnyashchiy (&) Á I.V. Ryjenko Á  ...  VLSI chip.  ... 
doi:10.1007/978-3-319-62870-7_25 fatcat:trwi3t75fvcslom3co5ziyxgpy

A 390-mm/sup 2/, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture

T. Kirihata, G. Mueller, B. Ji, G. Frankowsky, J.M. Ross, H. Terletzki, D.G. Netis, O. Weinfurtner, D.R. Hanson, G. Daniel, L.L.-C. Hsu, D.W. Sotraska (+7 others)
1999 IEEE Journal of Solid-State Circuits  
These features result in a 1.6-Gb/s data rate for 2 2 232 200-MHz DDR operation with a cell/chip area efficiency of 67.5%.  ...  Two of the LBL pairs are coupled to the SA by wiring over two other LBL pairs using hierarchical bitlines. This results in a reduction of the number of the SA's to 1/4, reducing the chip size by 6%.  ...  Mendes for the 200-MHz DDR operation used for this paper.  ... 
doi:10.1109/4.799866 fatcat:zwrjvjrsibervcs5erg74bfn5m
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